References. References. 네트워크 프로세서 개요 (Network Processor Overview) Traditional Network System

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1 이 강좌는 연세대학교 이용석 교수 연구실에서 제작되었으며 copyright가 없으므로 비영리적인 목적에 한하여 누구든지 복사, 배포가 가능합니다. 연구실 홈페이지에는 고성능 마이크로프로세서에 관련된 많은 강좌가 있으며 누구나 무료로 다운로드 받을 수 있습니다. 연세대학교 전기전자공학과 프로세서 연구실 박사과정 홍인표 네트워크 프로세서 개요 (Network Processor Overview) 연세대학교 이용석교수 연구실 박사과정 홍 인 표 Homepage: 전화: : References 1. Douglas E. Comer, Network Systems Design Using Network Processors, 2004, Pearson Prentice Hall 2. Microprocessor Report, Cahners, ~ References 3. White papers and presentations of network processor makers: Presentations from Network Processor Summit in Networld+Interop,, Las Vegas, Traditional Network System Embedded Processors Large and complex layer 4 protocol Interface1 Layer 4 Embedded processor Layer 1 & 2 Layer 3 & class. ASIC Standard CPU Other processing Traffic Mgmt. (ASIC) Switching Fabric Layer 4 Embedded processor Interface2 Layer 3 & class. Layer 1 & 2 ASIC 4 1

2 Traditional Network System What is the Network Processor? ASIC Growth of network data rates OC-3, OC-12, OC-48, OC-192 Bottleneck: embedded processor The only solution for high-speed backbone Problem High cost Long time-to to-market Difficult to simulate Hard to debug, change or reuse 5 Performance ASIC Network Processor General Purpose up High-speed & Flexible Flexibility & time-to-market 6 What is the Network Processor? Traffic 증가 음성, 데이터 통합 다양한 네트워크 서비스 등장 늘어나는 traffic을 감당할 수 있으면서, 유연하게 신기술에 대응할 수 있는 네트워크 장비 High-performance Programmable Network devices 7 Requirements High performance processing Flexibility Ability to leverage co-processors & memory Headroom for emerging services Robust software development environment 8 What is Important in NPUs Performance Gap Performance & Scalability Parallel architecture Pipelining Flexibility Programmability Programmability Software controls hardware 9 Speed of Internet Backbone Connections (Mbps) 62500Mbps 12500Mbps 2500Mbps 500Mbps 100Mbps T1 OC-3 OC-12 OC-48 OC-768 OC MIPS 12500MIPS 2500MIPS 500MIPS 100MIPS CPU Speed (MIPS) 10 2

3 Architecture Types of Network Processors 12 stream F( ) G( ) H( ) I( ) Pipeline architecture stream Classify Lookup Modify Queueing RISC RISC RISC RISC stream F( ); G( ); H( ); I( ) F( ); G( ); H( ); I( ) F( ); G( ); H( ); I( ) Parallel architecture 11 Pipeline Approach High performance Multiple Processor Approach Flexibility Time-to to-market Source: Networld+Interop 2000 Pipeline Processing Approach Example) TOPs of EZchip External Policy Co-Processor Interface External TOPmodify: : header and content modification Streams Parsing Searching Editing Queuing/ Fabric Scheduling TOPresolve: : Queue management and forwarding buffer TOPsearch: : Table lookup Output Scheduling Streams Editing Egress Lookup Fabric Enqueuing TOPparse: : Header field extraction and classification Co-Processor Interface External 13 * TOP: Task Optimized Processor 14 Example) TOPs of EZchip Switching Fabric Queuing Example) PXF of Cisco 32 homogeneous embedded processors modify MAC classify resolve Accounting & ICMP FIB & Netflow search MPLS classify Access Control parse CAR routing MLPPP MAC Network 15 output WRED 16 3

4 Multiple Processor Approach Multiple Processor Approach Source: Networld+Interop Source: CSIX & CPIX 18 Example) BCM1250 of Broadcom Dual 1GHz MIPS 64 Processor Example) CNP810 of Clearwater Networks Use a SMT core instead of multiple processors JTAG Debug/ Bus Trace SB-1 Core SB-1 Core L2 Cache Data Mover Cache DDR1 DMA1 DDR2 DMA2 DDR3 DMA3 DDR4 DMA4 PCI-X Serial Interface Serial Interface D M A D M A 256 Bits DDR ZBbus Controller SPI-4 SPI-3 Xpress Switch (peak 225Gbps) UART1 UART2 Dual I/O Bridge DMA DMA DMA SMBus 10/100/ 10/100/ 10/100/ Generic Bus GPIO/ And Interrupt/ MAC MAC MAC Flash I/O PCMCIA FIFO FIFO Source: PCI/HT Bridge 32-Bit PCI HT Host Bridge 19 SPI-3 PMU (PMMU, Queues) RTU SMT Core SPI EEPROM JTAG & Trace 20 Example) CNP810 of Clearwater Networks Example) IXP-2800 of Intel Reference about SMT core 온라인 강좌 SMT 마이크로프로세서 구조의 개요 Thread context Register file Thread context Register file Thread context Register file Thread context Register file Program counter Program counter Program counter Program counter Execution resources ALUs Multipliers FPUs

5 More Commercial Network Processors Reference [1] Chapter 15 Instruction Set Architecture Dedicated instruction set Network specific ISA Modified RISC instruction set MIPS ISA + special instructions Instruction Set Architecture Dedicated instruction set Small fast instruction set Less than 40 instructions Strong bit manipulation Bit field extraction Special functions; CRC or Hash Load/store on various data sizes Load/store on various kind of memories Conditional branch Different conditions from common RISCs 25 Dedicated Instruction Set Arithmetic, rotate, and shift ALU Arithmetic operation ALU_SHF Arithmetic operation and shift Field extraction DBL_SHF Concatenate two words and shift 26 Dedicated Instruction Set Dedicated Instruction Set Branch Common conditional branch BR_BSET, BR_BCLR Branch if bit set or clear BR=BYTE, BR!=BYTE Branch if byte equal or not equal Branch on event or signal Common jump and return 27 Reference CSR FIFO PCI bus Scratchpad memory SDRAM SRAM 28 5

6 Dedicated Instruction Set Dedicated Instruction Set Local register instructions FIND_BSET (_WITH_MASK) IMMED IMMED_Bn, IMMED_Wn LD_FIELD (_W_CLR) LOAD_ADDR LOAD_BSET_RESULTn 29 Misc. HASH NOP CTX_ARB Context swap and wake on event 30 Instruction Set Architecture Modified RISC ISA Modified RISC ISA Mostly based on MIPS ISA Remove some instructions Add network specific instructions Example) Clearwater networks, CNP810 Motorola C-5C Broadcom BCM ISA of Motorola C-5C MIPS based ISA Removed instructions Multiply, divide FPU instructions Unaligned load/store Move to high/low Added instructions CLZ Insert/extract bit field Conditional branches 32 Data Transfer Subsystem Intensive data movement Subsystem Internal Transfer Mechanism Streaming data Not reused Not suitable for cache On-chip SRAM buffer External Interfaces 33 Cache + special hardware Ex) Management Unit 34 6

7 Subsystem Subsystem Table data Various lookup tables L3 Routing table, L2 forwarding, security policy table, and etc. address SRAM contents CAM Compare hit Cache memory data = data CAM (Content Addressable ) Suitable for table lookup Small capacity Internal Transfer Mechanism Internal Transfer Mechanism Internal bus Hardware FIFO On-chip shared memory Internal bus Multiple units are attached to an internal bus Centralized control (bus arbiter) Multiple DMA engines 256~512bits wide Internal Transfer Mechanism External Interfaces Hardware FIFO stream FIFO FIFO FIFO Classify Lookup Modify Queueing 39 Standard and specialized bus interfaces USB, PCI, LA-2 2 (by NPF) External memory interfaces Direct I/O interfaces SPI, SFI, serial line Switching fabric interfaces CSIX standard 40 7

8 External Interfaces External memory Fast DRAM DDR-SDRAM QDR-SDRAM CNP810, BCM-1250 RDRAM IXP2400, IXP2800 bandwidth NPUs > General Purpose Processors 41 Example) Data Transfer Units of CNP810 Direct I/O interface On-chip memory Cache SPI-4 SPI-3 SPI-3 DDR1 DMA1 Xpress Switch (peak 225Gbps) PMU (PMMU, Queues) High-speed external memory DDR2 DMA2 RTU DDR3 DMA3 DDR4 DMA4 SMT Core Internal bus interface PCI-X UART1 UART2 SPI EEPROM JTAG & Trace Direct I/O interface Management Unit 42 Benchmarks Netbench Hard to compare the performance of network processors Various target application range Various operating environment Netbench cares.icsl.ucla.edu/netbench/ Commbench ccrc.wustl.edu/~wolf/cb/ 43 Micro-level algorithms CRC: CRC32 TL: Table Lookup (radix-tree routing table) IP-level algorithms Route: IPv4 routing DRR: scheduling method NAT: Network Address Translation IPCHAINS: firewall application Application-level level algorithms URL: URL-based switching DH: public key encryption mechanism MD5: Message Digest algorithm (security) 44 Commbench Header processing applications RTR: Radix-Tree Routing table lookup FRAG: IP-packet fragmentation DRR: scheduling algorithm TCP: TCP traffic monitoring Payload processing applications CAST: CAST-128 block ciper algorithm ZIP: data compression REED: Reed-Solomon forward error correction JPEG 45 8