Counter/shift-register model. State machine model (cont d) General state machine model

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1 CSE 37 Spring 26 Introduction to igital esign Lecture 8: Moore and Mealy Machines Last Lecture Finite State Machines Today Moore and Mealy Machines Counter/shift-register model Values stored in registers represent the state of the circuit Combinational computes: function of current state and inputs values of flip-flops Inputs ext State Current State Outputs General state machine model State machine model Values stored in registers represent the state of the circuit Combinational computes: function of current state and inputs function of current state and inputs (Mealy machine) function of current state only (Moore machine) Inputs put Current State ext State Outputs States: S, S 2,..., S k Inputs: I, I 2,..., I m Outputs: O, O 2,..., O n Transition function: F s (S i, I j ) Output function: F o (S i ) or F o (S i, I j ) ext State Inputs put Current State State Clock ext State Outputs

2 Comparison of Mealy and Moore machines Mealy machines t to have less states different on arcs (n 2 ) rather than states (n) Moore machines are safer to use change at clock edge (always one cycle later) in Mealy machines, input change can cause put change as soon as is done a big problem when two machines are interconnected asynchronous feedback may occur if one isn t careful Mealy machines react faster to inputs react in same cycle don't need to wait for clock in Moore machines, more may be necessary to decode state into more gate delays after clock edge Comparison of Mealy and Moore machines Moore Mealy inputs inputs Synchronous Mealy combinational for state feedback for combinational for state feedback inputs reg reg for combinational for state feedback for reg reset / Specifying for a Moore machine Output is only function of state specify in state bubble in state diagram example: sequence detector for or / C/ / E/ current next reset input state state put C C E C C E C E E reset/ Specifying for a Mealy machine Output is function of state and inputs specify put on transition arc between states example: sequence detector for or / / / / C / / current next reset input state state put C C C C C

3 Registered Mealy machine (really Moore) Synchronous (or registered) Mealy machine registered state avoids glitchy easy to implement in PLs Moore machine with no put decoding computed on transition to rather than after entering view as expanded state vector Inputs put Outputs Example: ving machine Release item after 5 cents are deposited Single coin slot for dimes, nickels o change Coin Sensor Reset Ving Machine FSM Clock Open Release Mechanism Current State Example: ving machine Suitable abstract representation tabulate typical input sequences: 3 nickels nickel, dime dime, nickel two dimes draw state diagram: inputs:,, reset put: open chute assumptions: assume and asserted for one cycle each state has a self loop for = = (no coin) S7 S3 S8 S S4 S Reset S2 S5 S6 Example: ving machine Minimize number of states - reuse states whenever possible 5 Reset 5 + present inputs next put state state open symbolic state table

4 Example: ving machine Example: Moore implementation Uniquely encode states present state inputs put open Mapping to X X X X X X Open X X X = + + = OPE = Example: ving machine One-hot encoding present state inputs put open = = + 2 = = OPE = 3 Equivalent Mealy and Moore state diagrams Moore machine associated with state Reset [] 5 [] + [] 5 [] + Reset Reset Mealy machine associated with transitions Reset/ / / / / +/ 5 5 ( + Reset)/ / / / Reset /

5 Example: Mealy implementation Example: Mealy implementation Reset/ / / Reset/ / / 5 / / / +/ 5 Reset / Open X X X present state inputs put open OPE = = + + = OPE = = + + = make sure OPE is when reset by adding gate Ving machine: Moore to synch. Mealy OPE = creates a combinational delay after and change in Moore implementation This can be corrected by retiming, i.e., move flip-flops and through each other to improve delay OPE.d = ( + + )(' + ' + + ) = ' ' + ' Implementation now looks like a synchronous Mealy machine it is common for programmable devices to have FF at of Ving machine: Mealy to synch. Mealy OPE.d = OPE.d = ( + + )(' + ' + + ) = ' ' + ' Open.d Open.d X X X

6 Mealy and Moore examples Mealy and Moore examples Recognize, =, Mealy or Moore? Recognize, =, then, Mealy or Moore? clock clock clock clock HLs and Sequential Logic Flip-flops representation of clocks - timing of state changes asynchronous vs. synchronous FSMs structural view (FFs separate from combinational ) behavioral view (synthesis of sequencers not in this course) ata-paths = data computation (e.g., LUs, comparators) + registers use of arithmetic/al operators control of storage elements Example: reduce--string-by- Remove one from every string of s on the input Moore zero [] one [] twos [] / Mealy zero [] one [] / / /

7 Verilog FSM - Reduce s example Moore machine module reduce (clk, reset, in, ); input clk, reset, in; put ; parameter zero = 2 b; parameter one = 2 b; parameter twos = 2 b; reg ; reg [2:] state; reg [2:] next_state; // state variables clk) if (reset) state = zero; else state = next_state; state assignment (easy to change, if in one place) zero [] one [] twos [] Moore Verilog FSM or state) case (state) zero: // last input was a zero if (in) next_state = one; else next_state = zero; one: // we've seen one if (in) next_state = twos; else next_state = zero; twos: // we've seen at least 2 ones if (in) next_state = twos; else next_state = zero; case crucial to include all signals that are input to state determination case (state) zero: = ; one: = ; twos: = ; case module note that put deps only on state Mealy Verilog FSM module reduce (clk, reset, in, ); input clk, reset, in; put ; reg ; reg state; // state variables reg next_state; clk) if (reset) state = zero; else state = next_state; or state) case (state) zero: // last input was a zero = ; if (in) next_state = one; else next_state = zero; one: // we've seen one if (in) next_state = one; = ; else next_state = zero; = ; case module / zero [] one [] / / / Synchronous Mealy Machine module reduce (clk, reset, in, ); input clk, reset, in; put ; reg ; reg state; // state variables clk) if (reset) state = zero; else case (state) zero: // last input was a zero = ; if (in) state = one; else state = zero; one: // we've seen one if (in) state = one; = ; else state = zero; = ; case module

8 Finite state machines summary Models for representing sequential circuits abstraction of sequential elements finite state machines and their state diagrams inputs/ Mealy, Moore, and synchronous Mealy machines Finite state machine design procedure deriving state diagram deriving state transition table determining and put functions implementing combinational Hardware description languages

ECE232: Hardware Organization and Design. Part 3: Verilog Tutorial. http://www.ecs.umass.edu/ece/ece232/ Basic Verilog

ECE232: Hardware Organization and Design Part 3: Verilog Tutorial http://www.ecs.umass.edu/ece/ece232/ Basic Verilog module ();