Systemy RT i embedded Wykład 10 Interfejsy mikrokontrolerów, cz. II

Transcription

1 Systemy RT i embedded Wykład 10 Interfejsy mikrokontrolerów, cz. II Wrocław 2013

2 Plan CAN USB Ethernet

3 CAN

4 CAN interface Features: Serial, two-wire, differential interface Designed to be used in a harsh environment (like cars) Used for intra-car communication (up to 40m) Multi-Master architecture Asynchronous data transfer. Data transfer controlled by the master Half-duplex transmission Point to point transmission Data rate up to 1Mb/s

5 CAN interface Features: High reliability: Detection of transmission errors by each node Very high number of nodes: Up to 2038 with 11-bit identifier (CAN 2.0A and 2.0B) Up to 536 million with 29-bit identifier (CAN 2.0B) Bus access with bit arbitration

6 CAN Controller Area Network

7 CAN warstwy ISO/OSI There exists different application layers: CANopen, DeviceNet, SDS, J1939, NMEA 2000, EnergyBus, MilCAN,

8 CAN warstwa fizyczna CAN can be implemented in different media under one condition: each node has to be able to monitor its transmission Usually a differential twisted pair is used Synchronisation by NRZ and bit-stuffing

9 CAN Data frame

10 CAN ramka danych

11 CAN ramka danych

12 CAN arbitraŝ szyny Each frame begins with Arbitration ID used for bus access arbitration When two devices try to transmitt simultaneously then the Aribitration ID allow flawless resolving of the collision

13 CAN physical layer versions

14 CAN network topology

15 CAN transceiver

16 CAN in STM32F4 Features: Supports CAN protocol version 2.0 A, B Active Bit rates up to 1 Mbit/s Three transmit mailboxes Configurable transmit priority Two receive FIFOs with three stages Scalable filter banks

17 CAN in STM32F4

18 CAN in STM32F4 Operating modes

19 CAN in STM32F4 Transmission mailbox states

20 CAN in STM32F4 Receive FIFO state

21 CAN in STM32F4 Identifier filtering: In the CAN protocol the identifier of a message is not associated with the address of a node but related to the content of the message A transmitter broadcasts its message to all receivers On message reception a receiver node decides - depending on the identifier value - whether the software needs the message or not. If the message is needed, it is copied into the SRAM. If not, the message must be discarded without intervention by the software

22 CAN in STM32F4

23 CAN in STM32F4 Filtering example

24 USB

25 USB interface Features: Serial, two-wire, differential interface Designed to be used as a universal serial protocol Used for communication between devices (up to 4.8m) Single Master architecture Asynchronous data transfer. Data transfer controlled by the master Half-duplex transmission Point to point transmission Data rate up to 4.8Gb/s

26 Interfejs USB

27 Interfejs USB

28 Interfejs USB

29 Interfejs USB

30 Interfejs USB

31 Interfejs USB

32 Interfejs USB

33 Interfejs USB

34 Interfejs USB

35 Interfejs USB

36 Interfejs USB

37 Interfejs USB

38 Interfejs USB

39 Interfejs USB

40 Interfejs USB

41 Interfejs USB

42 Interfejs USB

43 USB - standards USB 1.1: Oryginal standard Up to 6 hosts and up to 127 nodes Master/Slave architecture Data rate: 1.5 Mb/s in LowSpeed 12 Mb/s in Full Speed Every node may get upto 500mA

44 USB - standards USB 2.0: Superseeds standard v 1.1 Main difference: HighSpeed mode with 480MB/s USB 3.0: Main difference: HighSpeed mode with 4.8 GB/s

45 USB class codes

46 Dziękuję za uwagę

47 FT232R Block diagram Dziękuję za uwagę

48 FT232R Dziękuję za uwagę

49 FT232R Autonomous supply Dziękuję za uwagę

50 USB 3.0

51 USB On the Go Features: USB OTG is a supplement to USB 2.0 or USB 3.0 specification It auguments the capability of USB peripherals by adding host functionality The switch between host and peripheral functionality can be made dynamically OTG devices must have Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) implemented

52 USB On the Go Requirements: A limited Host capability Full-speed operation as a peripheral (high-speed optional) Full-speed support as a host (low-speed and highspeed optional) Session Request Protocol Host Negotiation Protocol One, and only one connection: a Micro-AB receptacle Bus current of minimum 8mA

53 Host Negotiation Protocol

54 Host Negotiation Protocol Initial conditions are the A-Device operating as host (a_host state) and the B-Device operating as a peripheral (b_peripheral state) The A-Device has its pull-down resistors turned on The B-Device has its pull-up turned on The A-Device performs all the normal host duties

55 Host Negotiation Protocol The application running on the A-Device starts the HNP ball rolling by negating an internal signal called a_bus_req, indicating that it does not need to use the bus The A-Device suspends the bus (a_suspend state) stops all bus traffic for at least 3ms The A-Device is still operating as the host, so its pull-down resistors remain on

56 Host Negotiation Protocol Then the B-device transitions to the b_wait_acon state, meaning the B- Device waits for the ADevice to connect In this state the B-Device disconnects by turning its pullup resistor off and turning its pull-down resistors on

57 Host Negotiation Protocol After disconnecting, the B-Device waits in the b_wait_acon state for the A- Device to connect as a peripheral The ADevice, which is in the a_suspend state, detects the dual PD state, and transitions to the a_peripheral state

58 Host Negotiation Protocol The ADevice connects as a peripheral in the normal USB way, by powering its D+ pullup resistor This causes the B-Device to transition to the b_host state, and the role reversal is complete

59 OTG Device architecture

60 USB in STM32F4 Features: Full support (PHY) for the optional On-The- Go (OTG) protocol: Integrated support for A-B Device Identification Integrated support for host Negotiation Protocol (HNP) and Session Request Protocol (SRP) Supports dynamic host-peripheral switch of role Software-configurable to operate as: SRP capable USB FS Peripheral (B-device) SRP capable USB FS/LS host (A-device) USB On-The-Go Full-Speed Dual Role device

61 USB in STM32F4 Features: Dedicated RAM of 1.25 Kbytes with advanced FIFO control: Configurable partitioning of RAM space into different FIFOs for flexible and efficient use of RAM Each FIFO can hold multiple packets Dynamic memory allocation Guaranteed max USB bandwidth for up to one frame (1ms) without system intervention

62 USB in STM32F4 Features - host: Up to 8 host channels (pipes): each channel is dynamically reconfigurable to allocate any type of USB transfer. Built-in hardware scheduler holding: Up to 8 interrupt plus isochronous transfer requests in the periodic hardware queue Up to 8 control plus bulk transfer requests in the non-periodic hardware queue Management of a shared RX FIFO, a periodic TX FIFO and a nonperiodic TX FIFO for efficient usage of the USB data RAM

63 USB in STM32F4 Features - peripheral: 1 bidirectional control endpoint0 3 IN endpoints (EPs) configurable to support Bulk, Interrupt or Isochronous transfers 3 OUT endpoints configurable to support Bulk, Interrupt or Isochronous transfers Management of a shared Rx FIFO and a Tx-OUT FIFO for efficient usage of the USB data RAM Management of up to 4 dedicated Tx-IN FIFOs (one for each active IN EP) to put less load on the application Support for the soft disconnect feature.

64 USB in STM32F4 block diagram

65 USB in STM32F4 Operation: The USB OTG FS is clocked with 48 MHz clock The CPU reads and writes from/to the OTG FS core registers through the AHB peripheral bus The CPU submits data over the USB by writing 32-bit words to dedicated OTG_FS locations (push registers) The data are then automatically stored into Tx-data FIFOs configured within the USB data RAM

66 USB in STM32F4 Operation: The CPU receives the data from the USB by reading 32-bit words from dedicated OTG_FS addresses (pop registers) The data are then automatically retrieved from a shared Rx-FIFO configured within the 1.25 KB USB data RAM

67 USB in STM32F4 OTG functonality:

68 USB in STM32F4 OTG functionality ID line: The host or peripheral (the default) role is assumed depending on the ID input pin The ID line status is determined on plugging in the USB, depending on which side of the USB cable is connected to the micro-ab receptacle OTG functionality can be also changed with HNP protocol

69 USB in STM32F4 Peripheral functonality:

70 USB in STM32F4 Peripheral functionality: The OTG_FS core instantiates the following USB endpoints: Control endpoint 0: Bidirectional and handles control messages only Separate set of registers to handle in and out transactions 3 IN endpoints Each of them can be configured to support the isochronous, bulk or interrupt transfer type 3 OUT endpoints Each of them can be configured to support the isochronous, bulk or interrupt transfer type

71 USB in STM32F4 Host functonality:

72 USB in STM32F4 Host functionality: Host channels: The OTG_FS core instantiates 8 host channels Each host channel supports an USB host transfer (USB pipe) The host is not able to support more than 8 transfer requests at the same time If more than 8 transfer requests are pending from the application, the host controller driver (HCD) must re-allocate channels when they become available

73 USB in STM32F4 Host functionality: Host channel control through HCCHARx: Channel enable/disable Program the FS/LS speed of target USB peripheral Program the address of target USB peripheral Program the endpoint number of target USB peripheral Program the transfer IN/OUT direction Program the USB transfer type (control, bulk, interrupt, isochronous) Program the maximum packet size (MPS) Program the periodic transfer to be executed during odd/even frames

74 USB in STM32F4 Host functionality: Host channel transfer control through HCTSIZx: transfer size in bytes number of packets making up the overall transfer size initial data PID

75 USB in STM32F4 Host scheduler: The host core features a built-in hardware scheduler which is able to autonomously reorder and manage the USB transaction requests posted by the application At the beginning of each frame the host executes the periodic (isochronous and interrupt) transactions first, followed by the nonperiodic (control and bulk) transactions

76 USB in STM32F4 Host scheduler: The host processes the USB transactions through request queues (one for periodic and one for nonperiodic) Each request queue can hold up to 8 entries Each entry represents a pending transaction request from the application, and holds the IN or OUT channel number along with other information to perform a transaction on the USB

77 IEEE Ethernet

78 Ethernet interface Features: Serial, two-wire, differential interface Designed to be used for Local and Metropolitan Area Networks Used for communication between simple devices, computers and servers (range depends on topology) CSMA/CD used Synchronous data transfer. Clock encoded within signal

79 Ethernet interface Features: Full-duplex or Half-duplex transmission Point to point and point-to-multipoint transmission Data rate up to 40Gb/s Working on different media: Coax cable 10Base-2 Twisted pair 100Base-T, 1000Base-T Fiber 100Base-F, 1000Base-SX, 1000Base-LX

80 Ethernet interface OSI examples

81 Ethernet interface Physical layer (10Mbps,100Mbps, 1Gpbs): 10 Mbps, 100 Mbps, and 1 Gbps Ethernet technologies utilize a specific type of line coding referred to as 8B/10B Coding used for: DC Current Elimination Clocking Pysical layer (10Gbps): 64B/66B coding used

82 Ethernet interface Physical layer

83 10Base-T Physical signals

84 100Base-T Physical signals

85 Fiber versions Physical signals (NRZI)

86 Physical signals - Comparison

87 Ethernet interface Data Link Layer: The same for 10 BASE-X, 100 BASE-X, 1000 BASE-X (GigE) or 10GBASE-X (10 GigE) This layer is referred to as the Media Access Control (MAC) layer Frame:

88 Ethernet interface Data Link Layer frame fields: Destination and Source Address Fields: MAC addresses Frame Type: This field contains information that determines the format of the frame Data Field: This field contains the bulk of the frame. This is where the upper layer information is encapsulated FCS Field: This is the frame check sequence

89 Ethernet interface Network Layer: The network layer resides within the information field of the data link layer This layer contains individual computer addresses or Web site addresses Usually IP protocol is used

90 Ethernet interface Network Layer IP protocol: The overall role of IP is the routing of the packet from the source to the destination It does not keep track of numbers of packets or lost packets throughout the network As with the MAC layer, the IP layer contains a source address, a destination address, and an FCS

91 Ethernet interface Network Layer IP protocol: The total length field identifies the overall length of the information field. The overall length of theinformation field can range from 46 bytes to 1500 bytes

92 Ethernet schemat blokowy

93 MII interface data reception

94 MII interface data transmission

95 Ethernet MAC STE100P

96 STE100P - aplikacja

97 ETH in STM32F4 The Ethernet peripheral consists of: a MAC (media access control) controller media independent interface (MII) dedicated DMA controller

98 ETH in STM32F4 Features: Supports 10/100 Mbit/s data transfer rates with external PHY interfaces MII used Supports both full-duplex and half-duplex operations: Supports CSMA/CD Protocol for half-duplex operation Supports IEEE 802.3x flow control for full-duplex operation Preamble and start-of-frame data (SFD) insertion in Transmit, and deletion in Receive paths

99 ETH in STM32F4 Features: Automatic CRC and pad generation and stripping controllable on a per-frame basis Programmable frame length to support Standard frames with sizes up to 16 KB Separate 32-bit status returned for transmission and reception packets MDIO interface for PHY device configuration and management Separate transmission, reception, and control interfaces to the Application

100 ETH in STM32F4 Features: Two sets of FIFOs: a 2-KB Transmit FIFO with programmable threshold capability, and a 2- KB Receive FIFO with a configurable threshold (default of 64 bytes) Discards frames on late collision, excessive collisions, excessive deferral and underrun conditions Supports internal loopback on the MII for debugging

101 ETH in STM32F4 Block diagram:

102 ETH in STM32F4 SMI interface: The station management interface (SMI) allows the application to access any PHY registers through a 2-wire clock and data lines. The interface supports accessing up to 32 PHYs

103 ETH in STM32F4 SMI interface: Frame Write cycle

104 ETH in STM32F4 MII interface: The media-independent interface (MII) defines the interconnection between the MAC sublayer and the PHY for data transfer at 10 Mbit/s and 100 Mbit/s

105 ETH in STM32F4 MII interface: MII_TX_CLK: continuous clock that provides the timing reference for the TX data transfer. The nominal frequency is: 2.5 MHz at 10 Mbit/s speed; 25 MHz at 100 Mbit/s speed. MII_RX_CLK: continuous clock that provides the timing reference for the RX data transfer. The nominal frequency is: 2.5 MHz at 10 Mbit/s speed; 25 MHz at 100 Mbit/s speed. MII_TX_EN: transmission enable indicates that the MAC is presenting nibbles on the MII for transmission.

106 ETH in STM32F4 MII interface: MII_TXD[3:0]: transmit data is a bundle of 4 data signals driven synchronously by the MAC sublayer MII_CRS: carrier sense asserted by the PHY when either the transmit or receive medium is non idle MII_COL: collision detection - asserted by the PHY upon detection of a collision on the medium, remains asserted while the collision condition persists

107 ETH in STM32F4 MII interface: MII_RXD[3:0]: reception data is a bundle of 4 data signals driven synchronously by the PHY MII_RX_DV: receive data valid indicates that the PHY is presenting recovered and decoded nibbles on the MII for reception MII_RX_ER: receive error

108 ETH in STM32F4 RMII interface: The reduced media-independent interface (RMII) specification reduces the pin count from 16 to 7 Provides independent 2-bit wide (dibit) transmit and receive data paths and 50MHz clock

109 ETH in STM32F4 MAC layer functions: Data encapsulation (transmit and receive) Framing (frame boundary delimitation, frame synchronization) Addressing (handling of source and destination addresses) Error detection Media access management Medium allocation (collision avoidance) Contention resolution (collision handling)

110 ETH in STM32F4 MAC layer functions - two operating modes: Half-duplex mode: CSMA/CD algorithms used Full duplex mode: simultaneous transmission and reception without contention when all the following conditions are met: physical medium capability to support simultaneous transmission and reception exactly 2 stations connected to the LAN both stations configured for full-duplex operation

111 ETH in STM32F4 MAC frame format:

112 ETH in STM32F4 Ethernet interrupts: Two interrupt vectors: one dedicated to normal Ethernet operations MAC source DMA source second used only for the Ethernet wakeup event

113 Thank you for your attention

114 References [1] Reference Manual RM0090, [2] [3] TD_INTD_AN_01.pdf?SOURCES=DOWNLOAD [4] [5] [6] [7] [8] gital Encoding Formats