An Interrupt Scheduling Mechanism of Virtual Network Interface Card for Xen-Based System Liuzheng Lu 1, a, Runze Wan 2,1, b * and Jinrong He 3, c

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1 5th Iteratoal Coferece o Computer Sceces ad Automato Egeerg (ICCSAE 205) A Iterrupt Schedulg Mechasm of Vrtual Network Iterface Card for Xe-Based System Luzheg Lu, a, Ruze Wa 2,, b * ad Jrog He 3, c School of Computer, Hube Uversty of Educato, Wuha , Cha; 2 Co-Iovato Cetre of Elemetary Educato Iformato Techology Servces of Hube, Wuha , Cha. 3 Scece Computg ad Itellget Iformato Processg of Guagx Hgher Educato Key Laboratory, Guagx Teachers Educato Uversty, Nag a lzlu@mal.hue.edu.c, b ruzewa@26.com, c hejrog@63.com *I ths paper, Ruze Wa s the correspodg author. Keywords: vrtualzato; terrupt; latecy; vrtual buffer. Abstract. As oe of typcal paravrtualzato hypervsors, Xe has receved wdespread attetos especally ts scalg capablty uder some kds of workload. I ths paper, we focus o the problem that the most CPU resources are occuped by frequet terrupt from the NIC(Network Iterface Card) ad t wll cause bottleeck of the system for Xe. To allevate ths problem, ths paper proposes a adaptve terrupt latecy schedulg mechasm based o XEN, whch use the pollg or terrupt method accordace wth the queue legth of vrtual buffer wthout supplemetg ay addtoal processg ut. Also, the method ca guaratee dfferet qualty of servce to some extet by meas of the defto of the two types of prorty vrtual buffers. Smulato results show that the mechasm ca reduce CPU overhead sgfcatly ad mprove system performace effectvely. I. INTRODUCTION Vrtualzato techology s beg wdely used the test of hardware ad software, server cosoldato, securty ad dsaster recovery. Vrtualzato techology refers to the realzato of utlzato of hardware, whch ca maxmze a hardware etty to a set of logcal etty to meet the requremets of dfferet busess. From the pot of vew of hardware, the research of vrtualzato techology such as vrtual processor, vrtual devce ad vrtual memory are developg rapdly[]. The DMA vrtualzato s bult the North Brdge Chpset for the hardware realzato of vrtual IRQ. VT-d[2] techology s a kd of hardware asssted vrtualzato techology, whch ca be geerated from the I/O equpmet terrupt request accurately to specfy dfferet vrtual mache. Takg to accout the behavor of a vrtual mache may affect the allocato of resources of other vrtual maches, Gupta et al. [3] put forward a set of prmtves to esure performace solato, whch use XeMo to measuremet the resource cosumpto of each VM accurately ad adopt SEDF-DC scheduler to allocate the resource of CPU. VPE[4] proposes oe of the uclear separated to hadle the I/O operato request scheme for the low rate of utlzato of mult-core CPU, whch ca mprove the performace of vrtual I/O. NCQ[5] apples the mult-ed queue NIC to reorder the receved packet for mprovg I/O throughput. Credt[6] s a kd of proportoal far sharg of o preemptve schedulg algorthm, whch set the parameter doma schedulg weghts for clet operatg system doma to hadle the I/O request. Due to the use of terrupt mechasm, CPU wll stop the curret thread as the exteral etwork data arrved. However, frequet terrupto lead to the fully occuped of processg resources as the packets arrved cotually, whch wll result the poor performace. To resolve the problem, ths paper proposes a accordg to etwork busy degree automatc adjustmet. A automatc swtchg mode betwee I/O mechasm ad Vrtual system s mplemeted Xe, whch ca deal wth the 206. The authors - Publshed by Atlats Press 97

2 data the buffer queue legth of vrtual mache rather tha eed to crease addtoal processg uts. II. VIRTUALIZATION ARCHITECTURE OF XEN Xe s oe of the most wdely vrtualzato techology for vrtual servce applcato, the logc structure as show fgure. The framework allows ay o-modfcato devce drver to drve the doma performs depedetly the host. Fgure shows the archtecture of the Iter-Doma o Xe vrtual mache. Dom 0 s a prvleged doma, ad Dom U s a clet doma for customers. IDD s the drver doma, where provdes the devce drver for customers to vst the hardware. Fgure 2 shows the Xe etwork operatg mode. Whle Dom U eed to receve the packets from etwork, Dom 0 mmedately wrte ths part of the data a shared data structure sde, ad get through the evet chael to form Dom U. The, the Hypervsor checks the evet ad set up a aalog chael to the Dom U. Next, the sub operatg system regards t as a exteral terrupt, ad call the NIC drver terrupt hadler whch ca be captured by the Hypervsor. Evetually the packets ca be read shared memory. Fg. Iter-Doma o Xe vrtual mache Fg. 2 Vrtualzato archtecture of Xe At preset, the research of the I/O techque ofte focuses o the etwork throughput. But for other dcators,. e. the CPU overhead, s ot beg pad atteto. Actually, the applcatos of request-respose frequetly etwork servces, NIC should carry through the terrupto to otfy the CPU after recevg the packet. O the oe had, most of the CPU resources wll be frequetly terrupted by the arrval of the card. O the other had, lower prorty packets may ot be tmely mplemeted. Ths wll cause a buffer overflow of the etwork subsystem, ad the receved packet may be dropped. If ths stuato lasts loger, t wll eable etwork servce request to reach saturato quckly, ad packet forwardg throughput wll drop to zero. Fally, the system CPU resources are suspeded due to lack of other processes. Takg to accout the terrupto caused by CPU cotext swtchg overhead s very large, the etwork operatoal modes s modfed [7] by the followg methods. Frstly, after addg the NIC delay terrupt mechasm, a tmer hardware s added to cotrol the frequecy of processg requests Dom U. Secodly, oly oe etwork I / O request s occurred wth the tme terval of clock cotrol for sub operatg system. Thus, etre CPU overhead ca be shorte by cotrollg I / O 98

3 terrupt request. However, there are also the followg dsadvatages: () Modfcato of physcal frastructure ad the hardware cost; (2) Sce every cotext swtch CPU eed that all the data the buffer card ca be processed completely ad the to ext, t s ot flexble eough. (3) Dfferetated demads are ot beg take to accout accordace wth the dfferet QoS requremets of packets. III. MECHANISM OF INTERRUPT LATENCY OF NIC I ths paper, the ma dea s that frot ed of the vrtual buffer data fetch tme terval ca ot be set as a fxed tme terval, but adjusted dyamcally accordg to the amout of uset data buffers. Ths allows the CPU s able to arrage job executo pla terms of the terval sze for the ext cycle. Besdes, the tme spa of CPU processg ca be set adaptvely accordg to the overload status of buffers. If the queue s too log ad the job executo program of the CPU s ot very busy after adjustmet. The CPU processg legth ca be exteded to esure that the buffers ot beg overflowed durg the ext cycle. Defto : The umber of vrtual cards s.the queue legth of -th buffer s q ( =, 2,, ) wth the prorty weght w.ad the watg tme for -th queue s deoted as T. Defto 2: Each queue s eager for be scheduled as early as possble, the we defe the value of asprato: T q ε = w*l( * ) () T0 m [0,,, ] { q} where the legth ad the weght of each queue s cosdered the calculato. Assumg that the tme terval j-th cycle s T j, the CPU tme beg allocated for -th buffer ca be gve as the followg rule: ε j tj = * T j (2) ε = Therefore, the amout of packets that ca be processed by CPU s calculated by C( j) = tj * q. We ca dscuss two cases to desg the terrupt latecy mechasm: () If packets s = = q C( j) > 0, the packets all buffers are uprocessed ad the amout of resdual q C( j). Assumg that the average geerato rate of packets from physcal NIC to vrtual hosts s λ, the latest overload s as : (2) Otherwse, = T j+ λ Tj. The, the tme terval the ext cycle should be set λtj + [ q C( j)] = = C( j) q C( j) 0 deotes that the packets s processed completely buffers. Ad the terrupto wll be occurred whle some packets arrved the buffer. To avod frequet terrupto for CPU as soo as the packets arrvg, a threshold value of Q Thres ca be cosdered. Whe the buffer queue legth ad the threshold s reached, t wll geerate a terrupt request to the frot ed. (3) 99

4 IV. SIMULATION AND RESULTS We costruct the expermetal platform wth a vrtual host, whch carres a quad core processor Itel (R) core (TM) GHZ ad 4G memory. Dom 0 s boud to a CPU core, ad the remag three uclear s shared by other subsystems. The etwork evromet s set up by several Ggabt swtches, where ope source testg tool for etwork performace s stalled. The operatg system of Dom 0 s CetOS 5.3, ad drver Doma ad other three Guest Doma are equpped wth Ubutu 8.0. Fgure 3 shows the comparso of CPU overhead uder the crcumstaces of dfferet umber of vrtual maches, ad we focus o Dom 0 ad Dom U respectvely. For Dom 0, the dscrepacy s ot obvous whether make use of the schedule mechasm. For Dom U, wth the crease the umber of vrtual maches, the proposed schedulg polcy sgfcatly better tha whe ot use. Fgure 2 shows the comparso of the throughput wth dfferet umber of VMs. As ca be see from the fgure, the throughput by applyg our mechasm s ot reduced sgfcatly compared to the crcumstace wthout optmazato. Ths meas that our scheme ca decreases the umber of CPU terrupto, ad meawhle keep hgh throughput. Fg. 3 Comparso of overload of CPU Fg. 4 Comparso of the throughput V. CONCLUSION I ths paper, we focus o the problem that the most CPU resources are occuped by frequet terrupt from the NIC(Network Iterface Card). To allevate ths problem, ths paper proposes a adaptve terrupt latecy schedulg mechasm for Xe-Based System. Smulato results show that the mechasm ca reduce CPU overhead sgfcatly ad mprove system performace effectvely. ACKNOWLEDGMENT Ths work s supported by the project of Hube Co-Iovato Ceter of Iformato Techology Servce for Elemetary Educato. Ths work s also partly supported by Natural Scece Foudato of Hube Provce (No. 205CFB405) ad Scece Computg ad Itellget Iformato Processg of Guagx Hhgher Educato Key Laboratory (No. GXSCIIP20406). 200

5 REFERENCES [] Ludmla Cherkasova,Dwaker Gupta,et al. Comparso of the three CPU schedulers Xe. ACM Sgmetrcs Performace Evaluato Revew, Sep.2007,42-5. [2] U Gurav, R Shakh. Vrtualzato-A key feature of cloud computg. ACM ICWET, Mumba, Maharashtra, da, 200: [3] Gupta D, Cherkasova L, Garder R,etal. Eforcg performace solato across vrtual maches Xe. Proceedgs of ACM IFIP USENIX 7th Iteratoal Mddleware Coferece (Mddleware 06). Melboure, Australa, 2006: [4] Juxg Lu, Bulet Abal. Vrtualzato Pollg Ege(VPE): Usg Dedcated CPU Cores to A accelerate I/O Vrtualzato. ACM Proeeedgs of the 23rd teratoal Coferece o Supercomputg, [5] YougJ Yu, Dog Sh, Hyeosag Eom, Heo Youg Yeom. NCQ vs. I/O Seheduler: Prevetg Uexpected Msbehavors. ACM Trasactos o Storage(TOS), 200, 6(l):5-27. [6] Dego Ogaro, Ala L.Cox, Scott Rxer. Schedulg I/O vrtual mache motors. Proceedgs of the Fourth ACM SIGPLAN/SIGOPS Iteratoal Coferece o Vrtual Executo Evromets, [7] Yag Hogbo. A study of hgh performace etwork vrtualzato techque[d]. Shagha Jaotog Uversty,