SCR, 12 A, 15mA, 500 V, SOT78. Planar passivated SCR (Silicon Controlled Rectifier) in a SOT78 plastic package.

Transcription

1 Rev. 5 2 March 29 Product data sheet 1. Product profile 1.1 General description Planar passivated SCR (Silicon Controlled Rectifier) in a SOT78 plastic package. 1.2 Features and benefits High reliability High surge current capability High thermal cycling performance 1.3 Applications Ignition circuits Motor control Protection Circuits Static switching 1.4 Quick reference data Table 1. Quick reference Symbol Parameter Conditions Min Typ Max Unit V DRM repetitive peak V off-state voltage I T(AV) I T(RMS) average on-state current RMS on-state current half sine wave; T mb 19 C; see Figure 3 half sine wave; T mb 19 C; see Figure 1; see Figure 2 Static characteristics I GT gate trigger current V D =12V; T j =25 C; I T =1mA; see Figure A A ma

2 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 K cathode 2 A anode 3 G gate mb mb anode mb A K G sym SOT78 (TO-22AB; SC-46) 3 3. Ordering information Table 3. Ordering information Type number Package Name Description Version TO-22AB; SC-46 plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-22AB SOT78 _5 Product data sheet Rev. 5 2 March 29 2 of 11

3 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 6134). Symbol Parameter Conditions Min Max Unit V DRM repetitive peak off-state - 5 V voltage V RRM repetitive peak reverse - 5 V voltage I T(AV) average on-state half sine wave; T mb 19 C; see Figure A current I T(RMS) RMS on-state current half sine wave; T mb 19 C; see Figure 1; see - 12 A Figure 2 di T /dt rate of rise of on-state I T =2A; I G =5mA; di G /dt = 5 ma/µs - 5 A/µs current I GM peak gate current - 2 A P GM peak gate power - 5 W T stg storage temperature C T j junction temperature C I TSM non-repetitive peak half sine wave; t p = 8.3 ms; T j(init) =25 C A on-state current half sine wave; t p = 1 ms; T j(init) =25 C; see - 12 A Figure 4; see Figure 5 I 2 t I2t for fusing t p = 1 ms; sine-wave pulse - 72 A 2 s P G(AV) average gate power over any 2 ms period -.5 W V RGM peak reverse gate voltage - 5 V 25 1aaa aaa999 I T(RMS) (A) 2 I T(RMS) (A) surge duration (s) T mb ( C) Fig 1. RMS on-state current as a function of surge duration; maximum values Fig 2. RMS on-state current as a function of mounting base temperature; maximum values _5 Product data sheet Rev. 5 2 March 29 3 of 11

4 15 3aab83 P tot (W) a = conduction angle (degrees) form factor a α I T(AV) (A) Fig 3. Total power dissipation as a function of average on-state current; maximum values 1 3 1aaa956 I TSM (A) dl T /dt limit 1 2 I T ITSM t p t T j initial = 25 C max t p (s) Fig 4. Non-repetitive peak on-state current as a function of pulse width for sinusoidal currents; maximum values _5 Product data sheet Rev. 5 2 March 29 4 of 11

5 16 3aab829 I TSM (A) I T ITSM t p t T j initial = 25 C max number of cycles Fig 5. Non-repetitive peak on-state current as a function of the number of sinusoidal current cycles; maximum values 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit R th(j-mb) thermal resistance from junction to mounting base see Figure K/W R th(j-a) thermal resistance from junction to ambient free air K/W 1 1aaa962 Z th(j-mb) (K/W) P t p δ = T t p t T t p (s) Fig 6. Transient thermal impedance from junction to mounting base as a function of pulse width _5 Product data sheet Rev. 5 2 March 29 5 of 11

6 6. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit Static characteristics I GT gate trigger current V D =12V; T j =25 C; I T = 1 ma; see ma Figure 8 I L latching current V D =12V; T j =25 C; see Figure ma I H holding current V D =12V; T j =25 C; see Figure ma V T on-state voltage I T =23A; T j = 25 C; see Figure V V GT gate trigger voltage I T = 1 ma; V D =12V; T j = 25 C; see V Figure 12 I T = 1 ma; V D =5V; T j = 125 C V I D off-state current V D =5V; T j = 125 C ma I R reverse current V R =5V; T j = 125 C ma Dynamic characteristics dv D /dt rate of rise of off-state V DM =335V; T j = 125 C; exponential V/µs voltage waveform; gate open circuit V DM =335V; T j =125 C; R GK = 1 Ω; exponential waveform; see Figure V/µs t gt t q gate-controlled turn-on time commutated turn-off time I TM =4A; V D = 5 V; I G = 1 ma; di G /dt = 5 A/µs; T j =25 C V DM =335V; T j =125 C; I TM =2A; V R =25V; (di T /dt) M =3A/µs; dv D /dt = 5 V/µs; R GK = 1 Ω µs µs 1 4 1aaa aaa952 dv D /dt (V/μs) I GT I GT(25 C) 1 3 (1) 2 (2) T j ( C) T j ( C) Fig 8. Normalized gate trigger current as a function of junction temperature Fig 7. Critical rate of rise of off-state voltage as a function of junction temperature; minimum values _5 Product data sheet Rev. 5 2 March 29 6 of 11

7 3 1aaa aaa95 I L I H I L(25 C) I H(25 C) Fig T j ( C) Normalized latching current as a function of junction temperature T j ( C) Fig 1. Normalized holding current as a function of junction temperature 3 1aaa aaa953 I T (A) V GT V GT(25 C) (1) (2) (3) V T (V) T j ( C) Fig 12. Normalized gate trigger voltage as a function of junction temperature Fig 11. On-state current as a function of on-state voltage _5 Product data sheet Rev. 5 2 March 29 7 of 11

8 7. Package outline Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-22AB SOT78 E p A A 1 D 1 q mounting base D L 1 (1) L 2 (1) L b 1 (2) (3 ) Q b 2 (2) (2 ) b(3 ) c e e 5 1 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A A b b 1 (2) b (2) 2 c D D 1 E e L L 1 (1) L 2 (1) max p q Q Notes 1. Lead shoulder designs may vary. 2. Dimension includes excess dambar. OUTLINE VERSION SOT78 REFERENCES IEC JEDEC JEITA 3-lead TO-22AB SC-46 EUROPEAN PROJECTION ISSUE DATE Fig 13. Package outline SOT78 (TO-22AB) _5 Product data sheet Rev. 5 2 March 29 8 of 11

9 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes _ Product data sheet - BT151_SER_L_R_4 Modifications: Package outline updated. Type number separated from data sheet BT151_SER_L_R_4. BT151_SER_L_R_ Product data sheet - BT151_SERIES_3 BT151_SERIES_3 ( Product specification - BT151_SERIES_ ) BT151_SERIES_ Product specification - BT151_SERIES_1 BT151_SERIES_ Product specification - - _5 Product data sheet Rev. 5 2 March 29 9 of 11

10 9. Legal information 9.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 9.3 Disclaimers General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 6134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 1. Contact information For more information, please visit: For sales office addresses, please send an to: _5 Product data sheet Rev. 5 2 March 29 1 of 11

11 11. Contents 1 Product profile General description Features and benefits Applications Quick reference data Pinning information Ordering information Limiting values Thermal characteristics Characteristics Package outline Revision history Legal information Data sheet status Definitions Disclaimers Trademarks Contact information Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. For more information, please visit: For sales office addresses, please send an to: Date of release: 2 March 29 Document identifier: _5