LT MHz to 2.7GHz High Linearity Direct Conversion Quadrature Demodulator DESCRIPTION FEATURES APPLICATIONS TYPICAL APPLICATION

Transcription

1 FEATURES Input Frequency Range:.8GHz to.7ghz* Ω Single-Ended and LO Ports High IIP: 8 at 9MHz,.6 at.9ghz High IIP: 4. at 9MHz, 6 at.9ghz Input P:. at 9MHz I/Q Gain Mismatch:.4 Typical I/Q Phase Mismatch:.4 Typical Low Output DC Offsets Noise Figure:.8 at 9MHz,.7 at.9ghz Conversion Gain: at 9MHz, 4. at.9ghz Very Few External Components Shutdown Mode 6-Lead QFN 4mm 4mm Package with Exposed Pad APPLICATIONS Cellular/PCS/UMTS Infrastructure ID Reader High Linearity Direct Conversion I/Q Receiver LT7 8MHz to.7ghz High Linearity Direct Conversion Quadrature Demodulator DESCRIPTION The LT 7 is an 8MHz to.7ghz direct conversion quadrature demodulator optimized for high linearity receiver applications. It is suitable for communications receivers where an signal is directly converted into I and Q baseband signals with bandwidth up to 49MHz. The LT7 incorporates balanced I and Q mixers, LO buffer amplifiers and a precision, high frequency quadrature phase shifter. The integrated on-chip broadband transformers provide Ω single-ended interfaces at the and LO inputs. Only a few external capacitors are needed for its application in an receiver system. The high linearity of the LT7 provides excellent spurfree dynamic range for the receiver. This direct conversion demodulator can eliminate the need for intermediate frequency (IF) signal processing, as well as the corresponding requirements for image filtering and IF filtering. Channel fi ltering can be performed directly at the outputs of the I and Q channels. These outputs can interface directly to channel-select fi lters (LPFs) or to baseband amplifi ers., LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. *Operation over a wider frequency range is possible with reduced performance. Consult the factory. TYPICAL APPLICATION BPF High Signal-Level I/Q Demodulator for Wireless Infrastructure LNA BPF INPUT LO INPUT ENABLE EN LO /9 V 9 LT7 I OUT I OUT Q OUT Q OUT 7 TA LPF LPF VGA VGA A/D A/D GAIN (), NF (), IIP () Conversion Gain, NF, IIP and IIP vs LO Input Power at 9MHz 4 C C IIP IIP DSB NF CONV GAIN LO INPUT POWER () 7 TAb IIP () 7f

2 LT7 ABSOLUTE MAXIMUM RATINGS (Note ) Power Supply Voltage...V Enable Voltage....V to.v LO Input Power... Input Power... Input DC Voltage...±.V LO Input DC Voltage...±.V Operating Ambient Temperature... 4 C to Storage Temperature Range... 6 C to C Maximum Junction Temperature... C CAUTION: This part is sensitive to electrostatic discharge (ESD). It is very important that proper ESD precautions be observed when handling the LT7. PIN CONFIGURATION 4 TOP VIEW I OUT I OUT Q OUT Q OUT LO EN VCC UF PACKAGE 6-LEAD (4mm 4mm) PLASTIC QFN T JMAX = C, θ JA = 7 C/W EXPOSED PAD (PIN #7) IS, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LT7EUF#PBF LT7EUF#TRPBF 7 6-Lead (4mm 4mm) QFN 4 C to Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. Consult LTC Marketing for information on nonstandard lead based fi nish parts. For more information on lead free part marking, go to: For more information on tape and reel specifi cations, go to: DC ELECTRICAL CHARACTERISTICS = V, T A = C, unless otherwise noted. (Note ) PARAMETER CONDITIONS MIN TYP MAX UNITS Supply Voltage 4.. V Supply Current ma Shutdown Current EN = Low < µa Turn On Time ns Turn Off Time 7 ns EN = High (On) V EN = Low (Off) V EN Input Current V ENABLE = V µa Output DC Offset Voltage f LO = 9MHz, P LO = < 9 mv ( I OUT I OUT, Q OUT Q OUT ) Output DC Offset Variation vs Temperature 4 C to 8 µv/ C 7f

3 AC ELECTRICAL CHARACTERISTICS Test circuit shown in Figure. (Notes, ) LT7 PARAMETER CONDITIONS MIN TYP MAX UNITS Input Frequency Range No External Matching (High Band). to.7 GHz With External Matching (Low Band, Mid Band).8 to. GHz LO Input Frequency Range No External Matching (High Band) With External Matching (Low Band, Mid Band). to.7.8 to. Baseband Frequency Range DC to 49 MHz Baseband I/Q Output Impedance Single-Ended 6Ω// pf GHz GHz Input Return Loss Z O = Ω,.GHz to.7ghz, > Internally Matched LO Input Return Loss Z O = Ω,.GHz to.7ghz, > Internally Matched LO Input Power to AC ELECTRICAL CHARACTERISTICS = V, EN = High, T A = C, P = ( /tone for -tone IIP and IIP tests), Baseband Frequency = MHz (.9MHz and.mhz for -tone tests), P LO =, unless otherwise noted. (Notes,, 6) PARAMETER CONDITIONS MIN TYP MAX UNITS Conversion Gain Voltage Gain, R LOAD = kω R F = 9MHz (Note ) R F = 9MHz R F = MHz R F = MHz 4.. Noise Figure (Double-Side Band, Note 4) R F = 9MHz (Note ) R F = 9MHz R F = MHz R F = MHz Input rd-order Intercept R F = 9MHz (Note ) R F = 9MHz R F = MHz R F = MHz Input nd-order Intercept R F = 9MHz (Note ) R F = 9MHz R F = MHz R F = MHz Input Compression R F = 9MHz (Note ) R F = 9MHz R F = MHz R F = MHz I/Q Gain Mismatch R F = 9MHz (Note ) R F = 9MHz R F = MHz R F = MHz I/Q Phase Mismatch R F = 9MHz (Note ) R F = 9MHz R F = MHz R F = MHz LO to Leakage R F = 9MHz (Note ) R F = 9MHz R F = MHz R F = MHz f

4 LT7 AC ELECTRICAL CHARACTERISTICS = V, EN = High, T A = C, P = ( /tone for -tone IIP and IIP tests), Baseband Frequency = MHz (.9MHz and.mhz for -tone tests), P LO =, unless otherwise noted. (Notes,, 6) PARAMETER CONDITIONS MIN TYP MAX UNITS to LO Isolation R F = 9MHz (Note ) R F = 9MHz R F = MHz R F = MHz c c c c Note : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note : Tests are performed as shown in the confi guration of Figure. Note : Specifications over the 4 C to 8 C temperature range are assured by design, characterization and correlation with statistical process control. Note 4: DSB Noise Figure is measured with a small-signal noise source at the baseband frequency of MHz without any fi ltering on the input and no other signal applied. Note : 9MHz performance is measured with external and LO matching. The optional output capacitors C-C4 (pf) are also used for best IIP performance. Note 6: For these measurements, the complementary outputs (e.g., I OUT, I OUT ) were combined using a 8 phase shift combiner. Note 7: Large-signal noise fi gure is measured at an output frequency of 98.7MHz with input signal at f LO MHz. Both and LO input signals are appropriately bandpass fi ltered, as well as baseband output. 4 7f

5 TYPICAL AC PEORMANCE CHARACTERISTICS LT7 = V, EN = High, T A = ºC, P = ( /tone for -tone IIP and IIP tests), f BB = MHz (.9MHz and.mhz for -tone tests), P LO =, unless otherwise noted. Test Circuit Shown in Figure (Note 6). GAIN (), NF (), IIP () Conversion Gain, NF and IIP vs Frequency LOW BAND 8 MID BAND IIP DSB NF CONV GAIN HIGH BAND 4 7 INPUT FREQUENCY (MHz) 4 C C 6 IIP () IIP vs Frequency 4 4 C C INPUT FREQUENCY (MHz) I CC (ma) Supply Current vs Supply Voltage C 4 C SUPPLY VOLTAGE (V) 7 G 7 G 7 G 4 Conversion Gain vs Input Power 9MHz.. I/Q Gain Mismatch vs Input Frequency f BB = MHz 4 C C I/Q Phase Mismatch vs Input Frequency f BB = MHz 4 C C CONVERSION GAIN () 9MHz MHz GAIN MISMATCH ()... PHASE MISMATCH (DEG). INPUT POWER () 7 G FREQUENCY (MHz) FREQUENCY (MHz) 7 G 7 G6 -LO ISOLATION (c) LO Isolation vs Input Power 9MHz 9MHz MHz LO- LEAKAGE () LO- Leakage vs LO Input Power MHz 9MHz 9MHz CONV. GAIN () 6 4 Conversion Gain vs Baseband Frequency f LO = 9MHz 4 C C INPUT POWER () G7 8 LO INPUT POWER () 7 G8.. BASEBAND FREQUENCY (MHz) 7 G9 7f

6 LT7 TYPICAL AC PEORMANCE CHARACTERISTICS = V, EN = High, T A = ºC, P = ( /tone for -tone IIP and IIP tests), f BB = MHz (.9MHz and.mhz for -tone tests), P LO =, unless otherwise noted. Test Circuit Shown in Figure (Note 6). GAIN (), NF (), IIP () Conversion Gain, IIP, NF vs LO Input Power at 9MHz f LO = 9MHz IIP DSB NF CONV GAIN LO INPUT POWER () 4 C C OUTPUT POWER (), IM () Output Power and IM vs Input Power at 9MHz f LO = 9MHz IM PRODUCT OUTPUT POWER 8 4 INPUT POWER () 4 C C 4 8 IIP () IIP vs LO Input Power at 9MHz f LO = 9MHz LO INPUT POWER () 4 C C 7 G 7 G 7 G GAIN (), NF (), IIP () Conversion Gain, IIP, NF vs LO Input Power at 9MHz f LO = 9MHz IIP DSB NF CONV. GAIN 4 C C LO INPUT POWER () OUTPUT POWER (), IM () Output Power and IM vs Input Power at 9MHz f LO = 9MHz IM PRODUCT OUTPUT POWER 8 4 INPUT POWER () 4 C C 4 8 IIP () IIP vs LO Input Power at 9MHz f LO = 9MHz 4 C C LO INPUT POWER () 7 G 7 G4 7 G GAIN (), NF (), IIP () 6 Conversion. Gain, IIP, NF vs LO Input Power at MHz f LO = MHz 4 C C IIP DSB NF CONV. GAIN LO INPUT POWER () 7 G6 OUTPUT POWER (), IM () Output Power and IM vs Input Power at MHz f LO = MHz OUTPUT POWER IM PRODUCT 8 4 INPUT POWER () 4 C C G7 IIP () IIP vs LO Input Power at MHz f LO = MHz LO INPUT POWER () 4 C C 7 G8 7f

7 LT7 TYPICAL AC PEORMANCE CHARACTERISTICS = V, EN = High, T A = ºC, P = ( /tone for -tone IIP and IIP tests), f BB = MHz (.9MHz and.mhz for -tone tests), P LO =, unless otherwise noted. Test Circuit Shown in Figure (Notes 6, 7)... I/Q Gain Mismatch vs LO Input Power f BB = MHz I/Q Phase Mismatch vs LO Input Power f BB = MHz 9MHz 9MHz MHz 8 6 Large-Signal DSB NF vs Input Power NOTE 7 GAIN MISMATCH ().... 9MHz MHz 9MHz PHASE MISMATCH (DEG) DSB NF () MHz 9MHz 9MHz. LO INPUT POWER () LO INPUT POWER () INPUT POWER () 7 G9 7 G 7 G RETURN LOSS () Port Return Loss LOW BAND; C = 4.7pF MID BAND; C = pf HIGH BAND; NO EXTERNAL COMPONENT FREQUENCY (MHz) RETURN LOSS () LO Port Return Loss LOW BAND; C =.9pF MID BAND; C =.pf HIGH BAND; NO EXTERNAL COMPONENT FREQUENCY (MHz) GAIN (), NF (), IIP () Conversion Gain, IIP, NF vs Supply Voltage IIP DSB NF CONV. GAIN 4.7V V.V FREQUENCY (MHz) 7 G 7 G 7 G4 7 6 IIP vs Supply Voltage 4.7V V.V.. I/Q Gain Mismatch vs Supply Voltage 4.7V V.V I/Q Phase Mismatch vs Supply Voltage 4.7V V.V IIP () 6 GAIN MISMATCH ()... PHASE MISMATCH (DEG) FREQUENCY (MHz) 7 G FREQUENCY (MHz) 7 G FREQUENCY (MHz) 7 G7 7f 7

8 LT7 TYPICAL AC PEORMANCE CHARACTERISTICS = V, EN = High, T A = ºC, P = ( /tone for -tone IIP and IIP tests), f BB = MHz (.9MHz and.mhz for -tone tests), P LO =, unless otherwise noted. Test Circuit Shown in Figure (Note 6). Conversion Gain Distribution at 9MHz IIP Distribution at 9MHz vs Temperature Noise Figure Distribution at 9MHz 4 4 T A = C 4 C C T A = C DISTRIBUTION (%) DISTRIBUTION (%) DISTRIBUTION (%) CONVERSION GAIN () IIP () DSB NOISE FIGURE () 7 G8 7 G9 7 G I/Q Amplitude Mismatch Distribution at 9MHz vs Temperature I/Q Phase Mismatch Distribution at 9MHz vs Temperature 6 4 C C 4 C C DISTRIBUTION (%) 4 DISTRIBUTION (%) AMPLITUDE MISMATCH (m) PHASE MISMATCH ( ) 7 G 7 G I-Output DC Offset Voltage Distribution vs Temperature Q-Output DC Offset Voltage Distribution vs Temperature 4 4 C C 4 4 C C DISTRIBUTION (%) DISTRIBUTION (%) DC OFFSET (mv) DC OFFSET (mv) G 7 G4 7f

9 LT7 PIN FUNCTIONS (Pins,, 4, 9, ): Ground pin. (Pin ): Input Pin. This is a single-ended Ω terminated input. No external matching network is required for the high frequency band. An external series capacitor (and/or shunt capacitor) may be required for impedance transformation to Ω in the low frequency band from 8MHz to.ghz (see Figure 4). If the source is not DC blocked, a series blocking capacitor should be used. Otherwise, damage to the IC may result. (Pins 6, 7, 8, ): Power Supply Pins. These pins should be decoupled using pf and.µf capacitors. EN (Pin ): Enable Pin. When the input voltage is higher than.v, the circuit is completely turned on. When the enable pin voltage is less than.v, the circuit is turned off. Under no conditions should the voltage at the EN pin exceed.v. Otherwise, damage to the IC may result. If the Enable function is not needed, then the EN pin should be tied to. LO (Pin ): Local Oscillator Input Pin. This is a singleended Ω terminated input. No external matching network is required in the high frequency band. An external shunt capacitor (and/or series capacitor) may be required for impedance transformation to Ω for the low frequency band from 8MHz to.ghz (see Figure 6). If the LO source is not DC blocked, a series blocking capacitor must be used. Otherwise, damage to the IC may result. Q OUT, Q OUT (Pins, 4): Differential Baseband Output Pins of the Q Channel. The internal DC bias voltage is.v for each pin. I OUT, I OUT (Pins, 6): Differential Baseband Output Pins of the I Channel. The internal DC bias voltage is.v for each pin. Exposed Pad (Pin 7): Ground Return for the Entire IC. This pin must be soldered to the printed circuit board ground plane. BLOCK DIAGRAM AMP I-MIXER LPF 6 I OUT I OUT LO BUFFERS /9 LO AMP LPF 4 Q OUT Q-MIXER Q OUT BIAS EXPOSED PAD EN 7 BD 7f 9

10 LT7 TEST CIRCUIT I OUT J C4 (OPT) C (OPT) J Q OUT I OUT J4 C (OPT) C (OPT) J6 Q OUT J C (OPT) I OUT EN I OUT Q OUT Q OUT LT7 VCC LO C nf C (OPT) J LO.6".8".8" r = 4.4 DC EN R K C7 nf C8.µF C9.µF 7 F REF DES VALUE SIZE PART NUMBER C, C7 pf 4 AVX 4CJAT C8.µF 4 AVX 4ZD4KAT C9.µF 6 AVX TPSAMOR8 R kω 4 FREQUENCY RANGE LOW BAND: 8 TO MHz MID BAND: TO MHz HIGH BAND: TO 7MHz MATCH LO MATCH BASEBAND C C C-C4 4.7pF.9pF pf pf pf.pf Figure. Evaluation Circuit Schematic 7 F 7 F Figure. Top Side of Evaluation Board Figure. Bottom Side of Evaluation Board 7f

11 LT7 APPLICATIONS INFORMATION The LT7 is a direct I/Q demodulator targeting high linearity receiver applications, such as ID readers and wireless infrastructure. It consists of transconductance amplifiers, I/Q mixers, a quadrature LO phase shifter, and bias circuitry. The signal is applied to the inputs of the transconductance amplifiers and is then demodulated into I/Q baseband signals using quadrature LO signals which are internally generated from an external LO source by precision 9 phase-shifters. The demodulated I/Q signals are single-pole low-pass filtered on-chip with a bandwidth of 49MHz. The differential outputs of the I-channel and Q-channel are well matched in amplitude; their phases are 9 apart. Broadband transformers are integrated on-chip at both the and LO inputs to enable single-ended and LO interfaces. In the high frequency band (.GHz to.7ghz), both and LO ports are internally matched to Ω. No external matching components are needed. For the lower frequency bands (8MHz to.ghz), a simple network with series and/or shunt capacitors can be used as the impedance matching network. Input Port Figure 4 shows the demodulator s input which consists of an integrated transformer and high linearity transconductance amplifiers. The primary side of the transformer is connected to the input pin. The secondary side of the transformer is connected to the differential inputs of the transconductance amplifiers. Under no circumstances should an external DC voltage be applied to the input pin. DC current flowing into the primary side of the transformer may cause damage to the integrated transformer. A series blocking capacitor should be used to AC-couple the input port to the signal source. The input port is internally matched over a wide frequency range from.ghz to.7ghz with input return loss typically better than. No external matching network is needed for this frequency range. When the part is operated at lower frequencies, however, the input return loss can be improved with the matching network shown in Figure 4. Shunt capacitor C and series capacitor C can be selected for optimum input impedance matching at the desired frequency as illustrated in Figure. For lower frequency band operation, the external matching component C can serve as a series DC blocking capacitor. INPUT EXTERNAL MATCHING NETWORK FOR LOW BAND AND MID BAND C PORT RETURN LOSS () C Figure 4. Input Interface C =.6pF; C = 4.7pF C =.9pF; NO SHUNT CAP NO EXTERNAL MATCHING FREQUENCY (GHz) 7 F Figure. Input Return Loss with External Matching TO I-MIXER TO Q-MIXER 7 F4 7f

12 LT7 APPLICATIONS INFORMATION The input impedance and S parameters (without external matching components) are listed in Table. Table. Input Impedance FREQUENCY INPUT S (GHz) IMPEDANCE (Ω) MAG ANGLE ( ).8 8. j j j j j j j j j j j j j j j j j j j j LO Input Port The demodulator s LO input interface is shown in Figure 6. The input consists of an integrated transformer and a precision quadrature phase shifter which generates and 9 phase-shifted LO signals for the LO buffer amplifiers driving the I/Q mixers. The primary side of the transformer is connected to the LO input pin. The secondary side of the transformer is connected to the differential inputs of the LO quadrature generator. Under no circumstances should an external DC voltage be applied to the input pin. DC current flowing into the primary side of the transformer may damage the transformer. A series blocking capacitor should be used to AC-couple the LO input port to the LO signal source. The LO input port is internally matched over a wide frequency range from.ghz to.7ghz with input return loss typically better than. No external matching network is needed for this frequency range. When the part is operated at a lower frequency, the input return loss can be improved with the matching network shown in Figure 6. Shunt capacitor C and series capacitor C can be selected for optimum input impedance matching at the desired frequency as illustrated in Figure 7. For lower frequency operation, external matching component C can serve as the series DC blocking capacitor. LO INPUT EXTERNAL MATCHING NETWORK FOR LOW BAND AND MID BAND C LO PORT RETURN LOSS () C LO Figure 6. LO Input Interface C =.6pF; C =.9pF LO QUADRATURE GENERATOR AND BUFFER AMPLIFIERS NO EXTERNAL MATCHING C =.6pF; NO SHUNT CAP FREQUENCY (GHz) 7 F7 Figure 7. LO Input Return Loss with External Matching 7 F6 7f

13 LT7 APPLICATIONS INFORMATION The LO input impedance and S parameters (without external matching components) are listed in Table. Table. LO Input Impedance FREQUENCY INPUT S (GHz) IMPEDANCE (Ω) MAG ANGLE ( ) j j j j j j j j j j j j j j j j j j j j..87. I-Channel and Q-Channel Outputs Each of the I-channel and Q-channel outputs is internally connected to through a 6Ω resistor. The output DC bias voltage is.v. The outputs can be DC-coupled or AC-coupled to the external loads. Each single-ended output has an impedance of 6Ω in parallel with a pf internal capacitor, forming a low-pass filter with a corner frequency at 49MHz. The loading resistance on each output, R LOAD (single-ended), should be larger than Ω to assure full gain. The gain is reduced by log ( 6Ω/R LOAD ) in when the output port is terminated by R LOAD. For instance, the gain is reduced by 7. when each output pin is connected to a Ω load (or Ω differentially). The output should be taken differentially (or by using differential-to-singleended conversion) for best performance, including NF and IM. The phase relationship between the I-channel output signal and the Q-channel output signal is fi xed. When the LO input frequency is larger (or smaller) than the input frequency, the Q-channel outputs (Q OUT, Q OUT ) lead (or lag) the I-channel outputs (I OUT, I OUT ) by 9. When AC output coupling is used, the resulting highpass fi lter s roll-off frequency is defi ned by the RC constant of the blocking capacitor and R LOAD, assuming R LOAD >> 6Ω. pf 6Ω 6Ω pf pf 6Ω 6Ω pf I OUT 6 I OUT Q OUT 4 Q OUT 7 F8 Figure 8. I/Q Output Equivalent Circuit 7f

14 LT7 APPLICATIONS INFORMATION Care should be taken when the demodulator s outputs are DC-coupled to the external load to make sure that the I/Q mixers are biased properly. If the current drain from the outputs exceeds 6mA, there can be signifi cant degradation of the linearity performance. Each output can sink no more than 6.8mA when the outputs are connected to an external load with a DC voltage higher than.v. The I/Q output equivalent circuit is shown in Figure 8. In order to achieve best IIP performance, it is important to minimize high frequency coupling among the baseband outputs, port and LO port. For a multilayer PCB layout design, the metal lines of the baseband outputs should be placed on the backside of the PCB as shown in Figures and. Typically, output shunt capacitors C-C4 are not required for the application near 9MHz. However, for other frequency bands, these capacitors can be optimized for best IIP performance. For example, when the operating frequency is 9MHz, the IIP can be improved to 4 or better when pf shunt capacitors are placed at each output. Enable Interface A simplifi ed schematic of the EN pin is shown in Figure 9. The enable voltage necessary to turn on the LT7 is V. To disable or turn off the chip, this voltage should be below V. If the EN pin is not connected, the chip is disabled. However, it is not recommended that the pin be left fl oating for normal operation. It is important that the voltage applied to the EN pin should never exceed by more than.v. Otherwise, the supply current may be sourced through the upper ESD protection diode connected at the EN pin. Under no circumstances should voltage be applied to the EN pin before the supply voltage is applied to the pin. If this occurs, damage to the IC may result. LT7 EN 6k 6k 7 F9 Figure 9. Enable Pin Simplifi ed Circuit 4 7f

15 LT7 PACKAGE DESCRIPTION UF Package 6-Lead Plastic QFN (4mm 4mm) (Reference LTC DWG # -8-69).7 ±. 4. ±.. ±..9 ±. (4 SIDES) PACKAGE OUTLINE. ±..6 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS BOTTOM VIEW EXPOSED PAD 4. ±..7 ±. R =. (4 SIDES) TYP 6 PIN TOP MARK (NOTE 6). ±. (4-SIDES) PIN NOTCH R =. TYP OR. 4 CHAMFER. ±.. REF.. NOTE:. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO- VARIATION (WGGC). DRAWING NOT TO SCALE. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.mm ON ANY SIDE. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN LOCATION ON THE TOP AND BOTTOM OF PACKAGE (UF6) QFN -4. ±..6 BSC Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 7f

16 LT7 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS Infrastructure LT4 Ultralow Distortion, IF Amplifi er/adc Driver 8MHz Bandwidth, 47 OIP at MHz,. to Gain Control Range with Digitally Controlled Gain LT.GHz to.ghz Direct Conversion Quadrature IIP, Integrated LO Quadrature Generator Demodulator LT6.8GHz to.ghz Direct Conversion Quadrature. IIP, Integrated LO Quadrature Generator Demodulator LT7 4MHz to 9MHz Quadrature Demodulator IIP, Integrated LO Quadrature Generator LT8 LT9 LT LT LT LT4 LT LT6 LT7 LT8 LT8.GHz to.4ghz High Linearity Direct Quadrature Modulator.7GHz to.4ghz High Linearity Upconverting Mixer.GHz to.ghz High Linearity Upconverting Mixer MHz to 7MHz High Linearity Upconverting Mixer 6MHz to.7ghz High Signal Level Downconverting Mixer Low Power, Low Distortion ADC Driver with Digitally Programmable Gain High Linearity, Low Power Downconverting Mixer High Linearity, Low Power Downconverting Mixer 4MHz to.7ghz High Signal Level Downconverting Mixer.GHz to.4ghz High Linearity Direct Quadrature Modulator 6MHz to MHz High Linearity Direct Quadrature Modulator.8 OIP at GHz, 8./Hz Noise Floor, Ω Single-Ended and LO Ports, 4-Channel W-CDMA ACPR = 64c at.4ghz 7. IIP at GHz, Integrated Output Transformer with Ω Matching, Single-Ended LO and Ports Operation.9 IIP at.9ghz, Integrated Output Transformer with Ω Matching, Single-Ended LO and Ports Operation 4. IIP at.9ghz, NF =.,.V to.v Supply, Single-Ended LO Port Operation 4.V to.v Supply, IIP at 9MHz, NF =., Ω Single-Ended and LO Ports 4MHz Bandwidth, 4 OIP, 4. to 7 Gain Control Single-Ended Ω and LO Ports, 7.6 IIP at 9MHz, I CC = 8mA V to.v Supply, 6. IIP, khz to GHz, NF =, I CC = 8mA, 6 LO- Leakage IIP =. and NF =. at 9MHz, 4.V to.v Supply, I CC = 78mA, Conversion Gain =.8 OIP at GHz, 9./Hz Noise Floor, Ω,.V DC Baseband Interface, 4-Channel W-CDMA ACPR = 66c at.4ghz.4 OIP at 9MHz, 8/Hz Noise Floor, kω,.v DC Baseband Interface, -Ch CDMA ACPR = 7.4c at 9MHz LT6 Ultra-Low Power Active Mixer ma Supply Current, IIP, NF, Usable as Up- or Down-Converter. LT68 7MHz to MHz High Linearity Direct.9 OIP at 8MHz, 6./Hz Noise Floor, Ω,.V DC Baseband Quadrature Modulator Interface, -Ch CDMA ACPR = 7.4c at 8MHz LT7.GHz to.ghz High Linearity Direct Quadrature Modulator.6 OIP at GHz, 8.6/Hz Noise Floor, High-Ohmic.V DC Baseband Interface, 4-Ch W-CDMA ACPR = 67.7c at.4ghz Power Detectors LTC Power Detectors with >4 Dynamic Range MHz to GHz, Temperature Compensated,.7V to 6V Supply LTC7 khz to MHz Power Detector khz to GHz, Temperature Compensated,.7V to 6V Supply LTC8 MHz to 7GHz Power Detector 44 Dynamic Range, Temperature Compensated, SC7 Package LTC9 MHz to GHz Power Detector 6 Dynamic Range, Low Power Consumption, SC7 Package LTC MHz to 7GHz Precision Power Detector Precision V OUT Offset Control, Shutdown, Adjustable Gain LTC MHz to 7GHz Precision Power Detector Precision V OUT Offset Control, Shutdown, Adjustable Offset LTC MHz to 7GHz Precision Power Detector Precision V OUT Offset Control, Adjustable Gain and Offset LT4 LTC6 MHz to GHz Log Power Detector with 6 Dynamic Range Precision 6MHz to 7GHz Power Detector with Fast Comparator Output ± Output Variation over Temperature, 8ns Response Time, Log Linear Response ns Response Time, Comparator Reference Input, Latch Enable Input, 6 to Input Range LT7 Wide Dynamic Range Log /IF Detector Low Frequency to GHz, 8 Log Linear Dynamic Range 6 LT 7 PRINTED IN USA Linear Technology Corporation 6 McCarthy Blvd., Milpitas, CA (48) 4-9 FAX: (48) LINEAR TECHNOLOGY CORPORATION 7 7f