1. Cyclone III Device Family Overview

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1 1. Cyclone III Device Family Overview July 2012 CIII CIII Cyclone III device amily oers a unique combination o high unctionality, low power and low cost. Based on Taiwan Semiconductor Manuacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and sotware eatures to minimize power consumption, Cyclone III device amily provides the ideal solution or your high-volume, low-power, and cost-sensitive applications. To address the unique design needs, Cyclone III device amily oers the ollowing two variants: Cyclone III lowest power, high unctionality with the lowest cost Cyclone III LS lowest power FPGAs with security With densities ranging rom about 5,000 to 200,000 logic elements (LEs) and 0.5 Megabits (Mb) to 8 Mb o memory or less than ¼ watt o static power consumption, Cyclone III device amily makes it easier or you to meet your power budget. Cyclone III LS devices are the irst to implement a suite o security eatures at the silicon, sotware, and intellectual property (IP) level on a low-power and high-unctionality FPGA platorm. This suite o security eatures protects the IP rom tampering, reverse engineering and cloning. In addition, Cyclone III LS devices support design separation which enables you to introduce redundancy in a single chip to reduce size, weight, and power o your application. This chapter contains the ollowing sections: Cyclone III Device Family Features on page 1 1 Cyclone III Device Family Architecture on page 1 6 Reerence and Ordering Inormation on page 1 12 Cyclone III Device Family Features Cyclone III device amily oers the ollowing eatures: Lowest Power FPGAs Lowest power consumption with TSMC low-power process technology and Altera power-aware design low Low-power operation oers the ollowing beneits: Extended battery lie or portable and handheld applications Reduced or eliminated cooling system costs Operation in thermally-challenged environments Hot-socketing operation support 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks o Altera Corporation and registered in the U.S. Patent and Trademark Oice and in other countries. All other words and logos identiied as trademarks or service marks are the property o their respective holders as described at Altera warrants perormance o its semiconductor products to current speciications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out o the application or use o any inormation, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version o device speciications beore relying on any published inormation and beore placing orders or products or services. ISO 9001:2008 Registered Cyclone III Device Handbook July 2012 Subscribe

2 1 2 Chapter 1: Cyclone III Device Family Overview Cyclone III Device Family Features Design Security Feature Cyclone III LS devices oer the ollowing design security eatures: Coniguration security using advanced encryption standard (AES) with 256-bit volatile key Routing architecture optimized or design separation low with the Quartus II sotware Design separation low achieves both physical and unctional isolation between design partitions Ability to disable external JTAG port Error Detection (ED) Cycle Indicator to core Provides a pass or ail indicator at every ED cycle Provides visibility over intentional or unintentional change o coniguration random access memory (CRAM) bits Ability to perorm zeroization to clear contents o the FPGA logic, CRAM, embedded memory, and AES key Internal oscillator enables system monitor and health check capabilities Increased System Integration High memory-to-logic and multiplier-to-logic ratio High I/O count, low-and mid-range density devices or user I/O constrained applications Adjustable I/O slew rates to improve signal integrity Supports I/O standards such as LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X, LVPECL, bus LVDS (BLVDS), LVDS, mini-lvds, RSDS, and PPDS Supports the multi-value on-chip termination (OCT) calibration eature to eliminate variations over process, voltage, and temperature (PVT) Four phase-locked loops (PLLs) per device provide robust clock management and synthesis or device clock management, external system clock management, and I/O interaces Five outputs per PLL Cascadable to save I/Os, ease PCB routing, and reduce jitter Dynamically reconigurable to change phase shit, requency multiplication or division, or both, and input requency in the system without reconiguring the device Remote system upgrade without the aid o an external controller Dedicated cyclical redundancy code checker circuitry to detect single-event upset (SEU) issues Nios II embedded processor or Cyclone III device amily, oering low cost and custom-it embedded processing solutions Cyclone III Device Handbook July 2012 Altera Corporation

3 Chapter 1: Cyclone III Device Family Overview 1 3 Cyclone III Device Family Features Wide collection o pre-built and veriied IP cores rom Altera and Altera Megaunction Partners Program (AMPP) partners Supports high-speed external memory interaces such as DDR, DDR2, SDR SDRAM, and QDRII SRAM Auto-calibrating PHY eature eases the timing closure process and eliminates variations with PVT or DDR, DDR2, and QDRII SRAM interaces Cyclone III device amily supports vertical migration that allows you to migrate your device to other devices with the same dedicated pins, coniguration pins, and power pins or a given package-across device densities. This allows you to optimize device density and cost as your design evolves. Table 1 1 lists Cyclone III device amily eatures. Table 1 1. Cyclone III Device Family Features Family Cyclone III Cyclone III LS Device Logic Elements Number o M9K Blocks Total RAM Bits 18 x 18 Multipliers PLLs Global Clock Networks Maximum User I/Os EP3C5 5, , EP3C10 10, , EP3C16 15, , EP3C25 24, , EP3C40 39, ,161, EP3C55 55, ,396, EP3C80 81, ,810, EP3C , ,981, EP3CLS70 70, ,068, EP3CLS , ,451, EP3CLS , ,137, EP3CLS , ,211, July 2012 Altera Corporation Cyclone III Device Handbook

4 1 4 Chapter 1: Cyclone III Device Family Overview Cyclone III Device Family Features Table 1 2 lists Cyclone III device amily package options, I/O pins, and dierential channel counts. Table 1 2. Cyclone III Device Family Package Options, I/O pin and Dierential Channel Counts (1), (2), (3), (4), (5) Family Package E144 (7) M164 P240 F256 U256 F324 F484 U484 F780 EP3C5 94, , , , 68 EP3C10 94, , , , 68 EP3C16 84, 19 92, , , , , , 140 Cyclone III (8) EP3C25 82, , , , , 83 EP3C40 128, , , , , 227 (6) EP3C55 327, , , 163 EP3C80 295, , , 181 EP3C , , 233 EP3CLS70 294, , , 181 Cyclone III LS EP3CLS , , , 181 EP3CLS , , 181 Notes to Table 1 2: EP3CLS , , 181 (1) For each device package, the irst number indicates the number o the I/O pin; the second number indicates the dierential channel count. (2) For more inormation about device packaging speciications, reer to the Cyclone III Package and Thermal Resistance webpage. (3) The I/O pin numbers are the maximum I/O counts (including clock input pins) supported by the device package combination and can be aected by the coniguration scheme selected or the device. (4) All packages are available in lead-ree and leaded options. (5) Vertical migration is not supported between Cyclone III and Cyclone III LS devices. (6) The EP3C40 device in the F780 package supports restricted vertical migration. Maximum user I/Os are restricted to 510 I/Os i you enable migration to the EP3C120 and are using voltage reerenced I/O standards. I you are not using voltage reerenced I/O standards, you can increase the maximum number o I/Os. (7) The E144 package has an exposed pad at the bottom o the package. This exposed pad is a ground pad that must be connected to the ground plane on your PCB. Use this exposed pad or electrical connectivity and not or thermal purposes. (8) All Cyclone III device UBGA packages are supported by the Quartus II sotware version 7.1 SP1 and later, with the exception o the UBGA packages o EP3C16, which are supported by the Quartus II sotware version 7.2. Cyclone III Device Handbook July 2012 Altera Corporation

5 Chapter 1: Cyclone III Device Family Overview 1 5 Cyclone III Device Family Features Table 1 3 lists Cyclone III device amily package sizes. Table 1 3. Cyclone III Device Family Package Sizes Family Package Pitch (mm) Nominal Area (mm 2 ) Length x Width (mm mm) Height (mm) E M P F Cyclone III Cyclone III LS U F F U F F U F Table 1 4 lists Cyclone III device amily speed grades. Table 1 4. Cyclone III Device Family Speed Grades (Part 1 o 2) Family Device E144 M164 P240 F256 U256 F324 F484 U484 F780 Cyclone III EP3C5 EP3C10 EP3C16 EP3C25, A7, A7, A7, A7 C8 C8 EP3C40 C8 EP3C55 EP3C80 C8, C8, C8, C8, EP3C120 C8, C8, C8, July 2012 Altera Corporation Cyclone III Device Handbook

6 1 6 Chapter 1: Cyclone III Device Family Overview Cyclone III Device Family Architecture Table 1 4. Cyclone III Device Family Speed Grades (Part 2 o 2) Family Device E144 M164 P240 F256 U256 F324 F484 U484 F780 Cyclone III LS EP3CLS70 EP3CLS100 EP3CLS150 EP3CLS200 Table 1 5 lists Cyclone III device amily coniguration schemes. Table 1 5. Cyclone III Device Family Coniguration Schemes Coniguration Scheme Cyclone III Cyclone III LS Active serial (AS) v v Active parallel (AP) v Passive serial (PS) v v Fast passive parallel (FPP) v v Joint Test Action Group (JTAG) v v Cyclone III Device Family Architecture Cyclone III device amily includes a customer-deined eature set that is optimized or portable applications and oers a wide range o density, memory, embedded multiplier, and I/O options. Cyclone III device amily supports numerous external memory interaces and I/O protocols that are common in high-volume applications. The Quartus II sotware eatures and parameterizable IP cores make it easier or you to use the Cyclone III device amily interaces and protocols. The ollowing sections provide an overview o the Cyclone III device amily eatures. Logic Elements and Logic Array Blocks The logic array block (LAB) consists o 16 logic elements and a LAB-wide control block. An LE is the smallest unit o logic in the Cyclone III device amily architecture. Each LE has our inputs, a our-input look-up table (LUT), a register, and output logic. The our-input LUT is a unction generator that can implement any unction with our variables. For more inormation about LEs and LABs, reer to the Logic Elements and Logic Array Blocks in the Cyclone III Device Family chapter. Cyclone III Device Handbook July 2012 Altera Corporation

7 Chapter 1: Cyclone III Device Family Overview 1 7 Cyclone III Device Family Architecture Memory Blocks Each M9K memory block o the Cyclone III device amily provides nine Kbits o on-chip memory capable o operating at up to 315 MHz or Cyclone III devices and up to 274 MHz or Cyclone III LS devices. The embedded memory structure consists o M9K memory blocks columns that you can conigure as RAM, irst-in irst-out (FIFO) buers, or ROM. The Cyclone III device amily memory blocks are optimized or applications such as high throughout packet processing, embedded processor program, and embedded data storage. The Quartus II sotware allows you to take advantage o the M9K memory blocks by instantiating memory using a dedicated megaunction wizard or by inerring memory directly rom the VHDL or Verilog source code. M9K memory blocks support single-port, simple dual-port, and true dual-port operation modes. Single-port mode and simple dual-port mode are supported or all port widths with a coniguration o 1, 2, 4, 8, 9, 16, 18, 32, and 36. True dual-port is supported in port widths with a coniguration o 1, 2, 4, 8, 9, 16, and 18. For more inormation about memory blocks, reer to the Memory Blocks in the Cyclone III Device Family chapter. Embedded Multipliers and Digital Signal Processing Support Cyclone III devices support up to 288 embedded multiplier blocks and Cyclone III LS devices support up to 396 embedded multiplier blocks. Each block supports one individual bit multiplier or two individual 9 9-bit multipliers. The Quartus II sotware includes megaunctions that are used to control the operation mode o the embedded multiplier blocks based on user parameter settings. Multipliers can also be inerred directly rom the VHDL or Verilog source code. In addition to embedded multipliers, Cyclone III device amily includes a combination o on-chip resources and external interaces, making them ideal or increasing perormance, reducing system cost, and lowering the power consumption o digital signal processing (DSP) systems. You can use Cyclone III device amily alone or as DSP device co-processors to improve price-to-perormance ratios o DSP systems. The Cyclone III device amily DSP system design support includes the ollowing eatures: DSP IP cores: Common DSP processing unctions such as inite impulse response (FIR), ast Fourier transorm (FFT), and numerically controlled oscillator (NCO) unctions Suites o common video and image processing unctions Complete reerence designs or end-market applications DSP Builder interace tool between the Quartus II sotware and the MathWorks Simulink and MATLAB design environments DSP development kits For more inormation about embedded multipliers and digital signal processing support, reer to the Embedded Multipliers in Cyclone III Devices chapter. July 2012 Altera Corporation Cyclone III Device Handbook

8 1 8 Chapter 1: Cyclone III Device Family Overview Cyclone III Device Family Architecture Clock Networks and PLLs Cyclone III device amily includes 20 global clock networks. You can drive global clock signals rom dedicated clock pins, dual-purpose clock pins, user logic, and PLLs. Cyclone III device amily includes up to our PLLs with ive outputs per PLL to provide robust clock management and synthesis. You can use PLLs or device clock management, external system clock management, and I/O interaces. You can dynamically reconigure the Cyclone III device amily PLLs to enable auto-calibration o external memory interaces while the device is in operation. This eature enables the support o multiple input source requencies and corresponding multiplication, division, and phase shit requirements. PLLs in Cyclone III device amily may be cascaded to generate up to ten internal clocks and two external clocks on output pins rom a single external clock source. For more PLL speciications and inormation, reer to the Cyclone III Device Data Sheet, Cyclone III LS Device Data Sheet, and Clock Networks and PLLs in the Cyclone III Device Family chapters. I/O Features Cyclone III device amily has eight I/O banks. All I/O banks support single-ended and dierential I/O standards listed in Table 1 6. Table 1 6. Cyclone III Device Family I/O Standards Support Type Single-Ended I/O Dierential I/O I/O Standard LVTTL, LVCMOS, SSTL, HSTL, PCI, and PCI-X SSTL, HSTL, LVPECL, BLVDS, LVDS, mini-lvds, RSDS, and PPDS The Cyclone III device amily I/O also supports programmable bus hold, programmable pull-up resistors, programmable delay, programmable drive strength, programmable slew-rate control to optimize signal integrity, and hot socketing. Cyclone III device amily supports calibrated on-chip series termination (R S OCT) or driver impedance matching (Rs) or single-ended I/O standards, with one OCT calibration block per side. For more inormation, reer to the I/O Features in the Cyclone III Device Family chapter. High-Speed Dierential Interaces Cyclone III device amily supports high-speed dierential interaces such as BLVDS, LVDS, mini-lvds, RSDS, and PPDS. These high-speed I/O standards in Cyclone III device amily provide high data throughput using a relatively small number o I/O pins and are ideal or low-cost applications. Dedicated dierential output drivers on the let and right I/O banks can send data rates at up to 875 Mbps or Cyclone III devices and up to 740 Mbps or Cyclone III LS devices, without the need or external resistors. This saves board space or simpliies PCB routing. Top and bottom I/O banks support dierential transmission (with the addition o an external resistor network) data rates at up to 640 Mbps or both Cyclone III and Cyclone III LS devices. Cyclone III Device Handbook July 2012 Altera Corporation

9 Chapter 1: Cyclone III Device Family Overview 1 9 Cyclone III Device Family Architecture For more inormation, reer to the High-Speed Dierential Interaces in the Cyclone III Device Family chapter. Auto-Calibrating External Memory Interaces Cyclone III device amily supports common memory types such as DDR, DDR2, SDR SDRAM, and QDRII SRAM. DDR2 SDRAM memory interaces support data rates up to 400 Mbps or Cyclone III devices and 333 Mbps or Cyclone III LS devices. Memory interaces are supported on all sides o Cyclone III device amily. Cyclone III device amily has the OCT, DDR output registers, and 8-to-36-bit programmable DQ group widths eatures to enable rapid and robust implementation o dierent memory standards. An auto-calibrating megaunction is available in the Quartus II sotware or DDR and QDR memory interace PHYs. This megaunction is optimized to take advantage o the Cyclone III device amily I/O structure, simpliy timing closure requirements, and take advantage o the Cyclone III device amily PLL dynamic reconiguration eature to calibrate PVT changes. For more inormation, reer to the External Memory Interaces in the Cyclone III Device Family chapter. Support or Industry-Standard Embedded Processors To quickly and easily create system-level designs using Cyclone III device amily, you can select among the 32-bit sot processor cores: Freescale V1 Coldire, ARM Cortex M1, or Altera Nios II, along with a library o 50 other IP blocks when using the system-on-a-programmable-chip (SOPC) Builder tool. SOPC Builder is an Altera Quartus II design tool that acilitates system-integration o IP blocks in an FPGA design. The SOPC Builder automatically generates interconnect logic and creates a testbench to veriy unctionality, saving valuable design time. Cyclone III device amily expands the peripheral set, memory, I/O, or perormance o legacy embedded processors. Single or multiple Nios II embedded processors are designed into Cyclone III device amily to provide additional co-processing power, or even replace legacy embedded processors in your system. Using the Cyclone III device amily and Nios II together provide low-cost, high-perormance embedded processing solutions, which in turn allow you to extend the lie cycle o your product and improve time-to-market over standard product solutions. 1 Separate licensing o the Freescale and ARM embedded processors are required. Hot Socketing and Power-On-Reset Cyclone III device amily eatures hot socketing (also known as hot plug-in or hot swap) and power sequencing support without the use o external devices. You can insert or remove a board populated with one or more Cyclone III device amily during a system operation without causing undesirable eects to the running system bus or the board that was inserted into the system. July 2012 Altera Corporation Cyclone III Device Handbook

10 1 10 Chapter 1: Cyclone III Device Family Overview Cyclone III Device Family Architecture The hot socketing eature allows you to use FPGAs on PCBs that also contain a mixture o 3.3-V, 2.5-V, 1.8-V, 1.5-V, and 1.2-V devices. The Cyclone III device amily hot socketing eature eliminates power-up sequence requirements or other devices on the board or proper FPGA operation. For more inormation about hot socketing and power-on-reset, reer to the Hot-Socketing and Power-on Reset in the Cyclone III Device Family chapter. SEU Mitigation Cyclone III LS devices oer built-in error detection circuitry to detect data corruption due to sot errors in the CRAM cells. This eature allows CRAM contents to be read and veriied to match a coniguration-computed CRC value. The Quartus II sotware activates the built-in 32-bit CRC checker, which is part o the Cyclone III LS device. For more inormation about SEU mitigation, reer to the SEU Mitigation in the Cyclone III Device Family chapter. JTAG Boundary Scan Testing Cyclone III device amily supports the JTAG IEEE Std speciication. The boundary-scan test (BST) architecture oers the capability to test pin connections without using physical test probes and captures unctional data while a device is operating normally. Boundary-scan cells in the Cyclone III device amily can orce signals onto pins or capture data rom pins or rom logic array signals. Forced test data is serially shited into the boundary-scan cells. Captured data is serially shited out and externally compared to expected results. In addition to BST, you can use the IEEE Std controller or the Cyclone III LS device in-circuit reconiguration (ICR). For more inormation about JTAG boundary scan testing, reer to the IEEE (JTAG) Boundary-Scan Testing or the Cyclone III Device Family chapter. Quartus II Sotware Support The Quartus II sotware is the leading design sotware or perormance and productivity. It is the only complete design solution or CPLDs, FPGAs, and ASICs in the industry. The Quartus II sotware includes an integrated development environment to accelerate system-level design and seamless integration with leading third-party sotware tools and lows. The Cyclone III LS devices provide both physical and unctional separation between security critical design partitions. Cyclone III LS devices oer isolation between design partitions. This ensures that device errors do not propagate rom one partition to another, whether unintentional or intentional. The Quartus II sotware design separation low acilitates the creation o separation regions in Cyclone III LS devices by tightly controlling the routing in and between the LogicLock regions. For ease o use, the separation low integrates in the existing incremental compilation low. For more inormation about the Quartus II sotware eatures, reer to the Quartus II Handbook. Cyclone III Device Handbook July 2012 Altera Corporation

11 Chapter 1: Cyclone III Device Family Overview 1 11 Cyclone III Device Family Architecture Coniguration Cyclone III device amily uses SRAM cells to store coniguration data. Coniguration data is downloaded to Cyclone III device amily each time the device powers up. Low-cost coniguration options include the Altera EPCS amily serial lash devices as well as commodity parallel lash coniguration options. These options provide the lexibility or general-purpose applications and the ability to meet speciic coniguration and wake-up time requirements o the applications. Cyclone III device amily supports the AS, PS, FPP, and JTAG coniguration schemes. The AP coniguration scheme is only supported in Cyclone III devices. For more inormation about coniguration, reer to the Coniguration, Design Security, and Remote System Upgrades in the Cyclone III Device Family chapter. Remote System Upgrades Cyclone III device amily oers remote system upgrade without an external controller. The remote system upgrade capability in Cyclone III device amily allows system upgrades rom a remote location. Sot logic (either the Nios II embedded processor or user logic) implemented in Cyclone III device amily can download a new coniguration image rom a remote location, store it in coniguration memory, and direct the dedicated remote system upgrade circuitry to start a reconiguration cycle. The dedicated circuitry perorms error detection during and ater the coniguration process, and can recover rom an error condition by reverting to a sae coniguration image. The dedicated circuitry also provides error status inormation. Cyclone III devices support remote system upgrade in the AS and AP coniguration scheme. Cyclone III LS devices support remote system upgrade in the AS coniguration scheme only. For more inormation, reer to the Coniguration, Design Security, and Remote System Upgrades in the Cyclone III Device Family chapter. Design Security (Cyclone III LS Devices Only) Cyclone III LS devices oer design security eatures which play a vital role in the large and critical designs in the competitive military and commercial environments. Equipped with the coniguration bit stream encryption and anti-tamper eatures, Cyclone III LS devices protect your designs rom copying, reverse engineering and tampering. The coniguration security o Cyclone III LS devices uses AES with 256-bit security key. For more inormation, reer to the Coniguration, Design Security, and Remote System Upgrades in Cyclone III Device Family chapter. July 2012 Altera Corporation Cyclone III Device Handbook

12 1 12 Chapter 1: Cyclone III Device Family Overview Reerence and Ordering Inormation Reerence and Ordering Inormation Figure 1 1 and Figure 1 2 show the ordering codes or Cyclone III and Cyclone III LS devices. Figure 1 1. Cyclone III Device Packaging Ordering Inormation Package Type E : Plastic Enhanced Quad Flat Pack (EQFP) Q : Plastic Quad Flat Pack (PQFP) F : FineLine Ball-Grid Array (FBGA) U : Ultra FineLine Ball-Grid Array (UBGA) M : Micro FineLine Ball-Grid Array (MBGA) Operating Temperature C : Commercial temperature (T J = 0 C to 85 C) I : Industrial temperature (T J = -40 C to 100 C) A : Automotive temperature (T J = -40 C to 125 C) Family Signature EP3C : Cyclone III Member Code 5 : 5,136 logic elements 10 : 10,320 logic elements 16 : 15,408 logic elements 25 : 24,624 logic elements 25E : 24,624 logic elements 40 : 39,600 logic elements 55 : 55,856 logic elements 80 : 81,264 logic elements 120 : 119,088 logic elements EP3C 25 F 324 C 7 N Package Code 144 : 144 pins 164 : 164 pins 240 : 240 pins 256 : 256 pins 324 : 324 pins 484 : 484 pins 780 : 780 pins Speed Grade 6 (astest) 7 8 Optional Suix Indicates speciic device options or shipment method N : Lead-ree packaging ES : Engineering sample Figure 1 2. Cyclone III LS Device Packaging Ordering Inormation Package Type F : FineLine Ball-Grid Array (FBGA) U : Ultra FineLine Ball-Grid Array (UBGA) Operating Temperature C : Commercial temperature (T J = 0 C to 85 C) I : Industrial temperature (T J = -40 C to 100 C) Family Signature EP3CLS : Cyclone III LS Member Code 70 : 70,208 logic elements 100 : 100,448 logic elements 150 : 150,848 logic elements 200 : 198,464 logic elements EP3CLS 70 F 484 C 7 N Package Code 484 : 484 pins 780 : 780 pins Speed Grade 7 (astest) 8 Optional Suix Indicates speciic device options or shipment method N : Lead-ree packaging ES : Engineering sample Cyclone III Device Handbook July 2012 Altera Corporation

13 Chapter 1: Cyclone III Device Family Overview 1 13 Document Revision History Document Revision History Table 1 7. Document Revision History Table 1 7 lists the revision history or this document. Date Version Changes July Updated 484 pin package code in Figure 1 1. December Updated Table 1 1 and Table 1 2. Updated Figure 1 1 and Figure 1 2. Updated hyperlinks. Minor text edits. December Minor text edits. July Minor edit to the hyperlinks. June October May Added Table 1 5. Updated Table 1 1, Table 1 2, Table 1 3, and Table 1 4. Updated Introduction, Cyclone III Device Family Architecture, Embedded Multipliers and Digital Signal Processing Support, Clock Networks and PLLs, I/O Features, High-Speed Dierential Interaces, Auto-Calibrating External Memory Interaces, Quartus II Sotware Support, Coniguration, and Design Security (Cyclone III LS Devices Only). Removed Reerenced Document section. Updated Increased System Integration section. Updated Memory Blocks section. Updated chapter to new template. Added 164-pin Micro FineLine Ball-Grid Array (MBGA) details to Table 1 2, Table 1 3 and Table 1 4. Updated Figure 1 2 with automotive temperature inormation. Updated Increased System Integration section, Table 1 6, and High-Speed Dierential Interaces section with BLVDS inormation. Removed the text Spansion in Increased System. Integration and Coniguration sections. Removed trademark symbol rom MultiTrack in MultiTrack Interconnect. July Removed registered trademark symbol rom Simulink and MATLAB rom Embedded Multipliers and Digital. Signal Processing Support section. Added chapter TOC and Reerenced Documents section. March Initial release. July 2012 Altera Corporation Cyclone III Device Handbook

14 1 14 Chapter 1: Cyclone III Device Family Overview Document Revision History Cyclone III Device Handbook July 2012 Altera Corporation

15 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Liecycle Inormation: Altera: EP3C25Q240C8N EP3CLS150F484N EP3C5E144C7N EP3CLS100F484C7 EP3C16E144C7 EP3C16F484C8 EP3C5F256C8 EP3CLS70F484C7N EP3C55F484 EP3CLS100F484C8N EP3C10E144C7 EP3C40F484C6 EP3C16U484C8 EP3C40F324A7N EP3C80F484C8 EP3C25F324A7N EP3C55U484C6 EP3C40U484C8 EP3C80F484N EP3C5U256C7 EP3C40F780C7 EP3C80F780 EP3C40F780C8N EP3CLS70F780N EP3C120F484C8N EP3C80U484C6N EP3C40F484N EP3C16U256C7N EP3CLS200F484C7 EP3C10M164N EP3C25E144C8 EP3C55F484C7N EP3C55F780C8N EP3C80F484C6N EP3CLS150F484C8 EP3C16F256C6 EP3C40F324 EP3C40Q240C8N EP3C25F256C7 EP3C16U256N EP3C25F256C8N EP3CLS100U484N EP3C10F256N EP3C10F256C6 EP3C120F484C7 EP3C25F324C8N EP3C55U484N EP3C5E144C7 EP3C25F324 EP3C25F256C8 EP3C16U484C6 EP3C16F484C6N EP3C55U484 EP3CLS150F484C7N EP3C80F484C7N EP3C40U484C6 EP3C25U256C8 EP3CLS150F484 EP3C55F484C7 EP3CLS100F780C7N EP3C5F256C6N EP3C5U256C6N EP3C120F484C8 EP3C80F780C8N EP3C80U484C8 EP3C16F484C6 EP3C16F484C7N EP3CLS70F780 EP3CLS100F780 EP3CLS100U484 EP3C5E144 EP3C25E144C7N EP3CLS200F484C8 EP3C55F780C8 EP3CLS70F484 EP3C25Q240C8 EP3C25F256C6N EP3CLS100F780C8N EP3C120F780C7 EP3CLS150F780C8 EP3CLS150F780N EP3C40F484C7N EP3C40U484N EP3C10F256 EP3C40Q240C8 EP3C55F780C6N EP3C80F484C6 EP3CLS70U484N EP3C16F256A7N EP3CLS200F780C7 EP3C16F256 EP3C55U484C7N EP3C10E144C8N EP3CLS70F780C7N EP3C10E144C8 EP3C80F780C6N EP3C5M164C8N EP3CLS200F780C8 EP3C40U484 EP3C10U256C8

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