Decoder Implementation Issues for Low Density Parity Check Convolutional Codes

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1 International Symposium on Information Theory and its Applications, ISITA24 Parma, Italy, October 3, 24 Decoder Implementation Issues for Low Density Parity Check Convolutional Codes Andrew Schaefer, Arvind Sridharan, Bernhard Koenig, Daniel J. Costello, Jr. Institute for Communications Engineering Munich University of Technology Department of Electrical Engineering University of Notre Dame Abstract With the aim of implementing decoders for low density parity check convolutional codes (LDPC-CC) in analog VLSI, we extend the investigations of []. We first provide further evidence of equivalent performance of digital and analog decoders by comparing probability density functions of output log-likelihood ratios and by examining the EXIT chart trajectories of each decoder type. Next we make use of the fact that the shape of an analog decoding trajectory depends on the relative delays between processing elements in the decoder. These delays in turn are dependent on the circuit layout. By assuming a simple circuit layout model in which the total delay is constrained to be a constant, we determine the distribution of delays that results in the fastest decoder. We obtain initial speed results from the EXIT charts, the accuracy of which we check with BER curves for particular signal to noise ratios (SNR) against simulation time. We finally provide two methods for predicting trajectories for the analog decoders from the characteristic curves only, thus saving computationally expensive simulations.. Introduction In [2] an algebraic construction of LDPC-CC s based on QC block codes was introduced. LDPC-CC s have sparse factor graph representations, making BP decoding feasible: in fact, high memory LDPC-CC s can be decoded in this fashion. Furthermore, LDPC-CC s can be decoded by a BP based sliding window decoder that outputs decoding results continuously. With timeinvariant LDPC-CC s, the regular graph structure of the LDPC-CC s can be exploited to implement decoding in analog using a simple rotating ring architecture []. This work was supported in part by NSF Grant CCR2-53, NASA Grant NAG and the state of Indiana Science and Technology Fund. Analog decoding involves the implementation of decoding algorithms for channel codes in analog VLSI (for overviews see, e.g., [3][4][5]). The core idea is that the operations performed at the check and variable nodes of a belief propagation decoder can be implemented with simple transistor circuits. This differs from a conventional time discrete decoder in that messages are passed between nodes as time continuous signals, such that we can talk of soft time decoding. Thus the analog decoder attempts to solve the set of non-linear equations represented by the factor graph in continuous rather than discrete time. In the paper we will also use the term time continuous decoder to refer to the analog decoder and the term time discrete decoder to refer to the digital decoder. After introducing some notation and terminology in section 2, section 3 compares the output probability density functions (pdfs) of the log-likelihood ratios (L-values) of each decoder type. We make further comparisons by examining decoder trajectories in section 4. In section 5 we show that circuit layout, which influences the delays between the processing nodes of the decoder, has a significant effect on convergence speed. We use EXIT charts as well as BER curves as tools for determining convergence speed and also introduce methods for predicting analog decoding trajectories. 2. Definitions and Preliminaries Let U GF (2) with elements {+, }, where + is the null element under addition. The L-value (or LLR) of U is defined as L(U) = log P (U = +) P (U = ) and P (U = ±) = e±l(u) + e ±L(U), () where P (U = u) denotes the probability that the random variable U takes on the value u. For descriptions of algebraically constructed LDPC- CCs, an introduction to the message passing algorithm used in decoders for these codes, and the fundamentals

2 #% $#!"#!.8.7 db digital analog ( & ' p(l(z)) db 3dB 5dB Figure : Structure of Rotating Ring Decoder. of analog decoding, we refer the reader to [] and the references therein. The proposed implementation idea for the analog rotating ring decoder is shown in figure. The decoding of bits at time t is based only on the received L-values in the window from time t K to time t + K. In the rotating ring design, we rotate both the position where the decoded L-values are read out and the position where new received L-values are written into the ring at the transmission rate. 3. Decoder Output Distributions For our analysis we considered a code of small memory to reduce the complexity of testing (in an actual implementation we would use a code with much larger memory to take full advantage of the power of LDPC- CCs). Its parity check matrix is given by [ ] D 3 D H(D) = D 5 D 2 D 4. (2) Output L-value distributions for analog and digital rotating ring decoders at different values of the channel SNR, E s /N, are shown in figure 2. We see that in all cases the L-value distributions show negligible differences. We have also performed tests for other codes which have given similar results. Finally, the results of [], where we compared BERs, also imply that the tails of the pdfs are close to identical. 4. Convergence Points of Trajectories in EXIT Charts Since the technique of EXIT charts is well established, we refer the reader to [6] for details. Briefly, based on the characteristic curves of component codes in a concatenated system, it is possible to predict iterative decoding performance. We do this for LDPC LLR L(z) Figure 2: Probability distributions of output L-values. L(z) is the output L-value and p(l(z)) is the pdf of the random variable L(z). I E,V L I A,V z - z - I A,C I E,C T I E,V L I A,V C R R C I A,C Figure 3: Schematic diagrams for the iterative decoders and points of measurements, L and T, for the extrinsic information on the EXIT charts. CC s by considering the set of variable nodes as one component decoder and the set of check nodes as the other. Referring to figure 3, we can model the time discrete decoder as having unit delay elements between the processing units (the mutual information I is labelled with A and E for apriori and extrinsic, respectively, and C and V for check node and variable node, respectively). Likewise we model the time continuous decoder as having a simple RC delay element between processing units. In each case, we can plot decoding trajectories by plotting the mutual information of extrinsic messages measured at points L and T on the figure at each time discrete step (for the time discrete decoder) or continuously (for the time continuous decoder). In terms of the rotating ring design, we use only extrinsic messages close to the read out point of the decoder as our mutual information points. A trajectory is obtained by doing multiple decoder runs. I E,C T

3 ) l v c= l 2).8.6 I B.4 2dB 4.dB l c v=(- l large.2 characteristic curves analog trajectories digital trajectories I A 3) small 4) ~ Figure 4: Average trajectories for analog and digital decoders for E s /N o of -4.dB and 2dB. In each case both decoder trajectories reach the same point, as by the intersection of the characteristic curves. Figure 5: Simplified circuit layout model ), with example layouts for different values of α, 2),3) and 4). Figure 4 shows two cases of channel SNR. We see that both types of decoders converge at the same points on the EXIT chart. 5. Using Circuit Layout to Enhance Analog Decoding Speed We now wish to gain some insight into how circuit layout can affect the speed of analog decoding. We use a simplified model where we assume equal wire lengths for all connections from variable to check nodes and equal wire lengths for all connections from check to variable nodes (one can imagine that we set all lengths equal to the average wire length for that connection type). We further constrain the system such that the sum of this average wire length is constant. A justification for using this average model is that in the LDPC- CC, the connection lengths between variable and check nodes are limited to the code memory and cannot span the whole length of the code. With reference to figure 5 (part ), we set up the following problem: We are given a fixed wiring length l that we arrange in the form of a square. The variable node and check node processing blocks may be placed anywhere on the square such that we assign a wire length l v c = αl for the variable to check node connections and a wire length l c v = ( α)l for the check to variable node connections. We now ask which α (, ) results in the fastest decoding convergence? Parts 2), 3) and 4) of figure 5 show some example layouts for different values of α. Note that in this experiment we are assuming the delay within the transistors themselves to be negligible. This assumption is supported by the fact that the interconnect length is increasingly a dominant factor in circuit design [7]. If we were, however, to take this extra delay into account, it would mean only that we have a smaller available design range of α. Since the resistance and capacitance of a wire are both proportional to the length of the wire, if RC is the delay associated with the total length of wire, then RC v c = α 2 RC and RC c v = ( α) 2 RC. Figure 6 shows how different EXIT trajectories are obtained for different values of α. We see, for example, that for α =., the trajectory hugs the characteristic curve of the variable node. Later, in figures and 2 we will plot the simulation time taken (as well as decoding time) to reach a point within a distance of.5 from the point (, ) on the EXIT chart. We use this as an indication of convergence and hence decoding speed. We see that the decoding speed is highest at α =.5. For asymmetrical designs, a smaller α results in a faster decoder than does a larger α. Tests at lower SNRs indicate similar results. 5.. Confirmation of Results with BER Curves If the method of determining decoder speed with EXIT charts is to be useful, it should be verified also through BER measurements. Figure 7 shows the BER against simulation time at E s /N = 2dB for various values of α. In figure 7 we see that after 25 time units we have the lowest BER for α =.3. Further

4 α =. 2.8 α=. α=.3 I B.6 contours of equal elapsed time BER 3 α=.6 α=.9.4 α =.9.2 characteristic curves I A Figure 6: EXIT trajectories for different values of α (dotted lines), points reached by different decoders at equal times (dashed lines), and bounds given by characteristic curves (outer solid lines). The top curve is for α =., the following curves are for increasing α in steps of.. emphasizing the need for proper circuit layout design, we see that the decoder with α =.3 reaches a BER of 4 about.5 times faster than the decoders with α =. and α =.9. The results compare reasonably well with those of the EXIT charts, although the EXIT charts indicate that the decoder with α =.5 is slightly faster than the decoder with α =.3 (this small difference compared to the BER results may be due to the definition of convergence assumed for the EXIT charts). To check that other SNR values do not have other optimal α, we performed an additional BER test at E s /N = 2.8dB, the results of which are shown in figure 8. Again we find a similar behaviour with respect to α and that a choice of α =.3 results in the fastest decoder (at a target BER of.6, this decoder is more than.5 times faster than the decoder having α =.9) Prediction of Analog EXIT Trajectories We now investigate two techniques for predicting analog decoding trajectories. Note that in a time discrete decoder, trajectory prediction means simply drawing a step function between the two characteristic curves. In the time continuous domain, this task is more demanding. The first technique (which we will refer to as method A), involves working with mutual information values normalised simulation time Figure 7: BER at E s /N o = 2dB as a function of decoding time for circuit layouts with varying values of α. BER α=. α=.3 α=.6 α= normalised simulation time Figure 8: BER at E s /N o = 2.8dB as a function of decoding time for circuit layouts with varying values of α. only. We view the decoder as only processing mutual information values, which are also exchanged between decoders through the RC delay elements. We now formalize the description. For the component decoders (which we label now as and 2) in a concatenation, we have I E = f (I A ) and I E2 = f 2 (I A2 ). Given the functions f (.) and f 2 (.), the evolution of the mutual informations in the discrete time algorithm can be by the equations I E,k+ = f (I A,k) and I E2,k+2 = f 2 (I A2,k+). (3) We can use these equations to formulate a fixed point

5 problem such that we are effectively looking for the I E that satisfies, I E = f 2 (f (I E )). (4) How we solve for the fixed point of equation (4) is our choice. One possibility is to use the method of successive substitution by applying the equations of (3). We may also introduce step sizes h and h 2 into (3) to obtain, I E,k+ = ( h ) I E,k + h f (I A,k), I E2,k+ = ( h 2 ) I E2,k + h 2 f 2 (I A2,k), (5) where the equations now run in parallel and I A,k = I E2,k and I A2,k = I E,k. Note again that we are operating directly on mutual information values. Now, we allow h and h 2 to tend to zero (and here we emphasize that the delays need not be uniform) to obtain the time continuous equations, τ di E τ 2 di E2 = f (I A ) I E, = f 2 (I A2 ) I E2 (6) where τ and τ 2 represent delay constants. Examining (6), and with I A,k = I E2,k and I A2,k = I E,k, we see that if die = and die = (i.e., the algorithm converges), then we have the same equation as (4). In the second technique (which we will refer to as method B), we no longer pass mutual information values through RC delay elements. Instead, the mutual information values are first converted to equivalent L- value means. These values are then passed through the RC delay elements and at the output they are converted to mutual information values again. Results are shown in figures 9 and. We see that for both prediction methods, the trajectories match reasonably well. Figures and 2 show the prediction of decoder speed against the actual decoder speed as measured using the EXIT chart. Here we note that, although the predictions are not exact, they show the same tendencies. Method A predicts that the fastest decoder has α =.5 and that this decoder requires half as much time as the slowest decoder to converge. Method B predicts the fastest decoder has α =.4 and that this decoder requires 3/4 as much time as the slowest decoder to converge (the EXIT chart results show that α =.5 gives the fastest decoder). Also of note in these figures is that prediction method B approximates the convergence time more accurately than method A. I T I L Figure 9: Simulated (solid line) and (dashed line, prediction method A) decoding trajectories for analog decoders having varying values of α. Results are for E s /N = 2dB. I T I L Figure : Simulated (solid line) and (dashed line, prediction method B) decoding trajectories for analog decoders having varying values of α. Results are for E s /N = 2dB. 6. Conclusions We have extended the results of [] and further demonstrated that analog implementations of LDPC- CC decoders produce equivalent results to their digital counterparts by comparing the probability distributions of the decoder output reliabilities. Additionally,

6 Normalised time Normalised time α α Figure : Simulated (solid line) and (dashed line) convergence times (prediction method A). Time is normalized such that the slowest decoder in each case, corresponding to α =.9, has the same speed. Results are for E s /N = 2dB. we have seen that, given a certain SNR, both digital and analog decoders converge to the same point on the EXIT chart as by the characteristic curves of the variable and check nodes. We then considered the effect of circuit layout on analog decoder speed, assuming a fixed wire length for interconnects which could be assigned freely between the check to variable connecting wires and the variable to check connecting wires. This simple experiment demonstrates that circuit layout can have a significant effect on decoder speed (up to a factor of approximately.5 as measured using a target BER). In particular, it is unwise to allow a large delay for the variable to check node connection. The same principle can be applied to all types of analog decoders for concatenated codes. A general rule seems to be to try and keep the delays between component decoders approximately the same. This depends, however, on the degree of asymmetry between the decoder characteristic curves. We see that EXIT chart trajectories give a good indication of decoder speed for various values of α. Finally, note that we have used a relatively simple delay model for this concatenated code, and it is certainly possible to construct more complicated models that are closer to actual circuit layout designs. References [] A. Schaefer, A. Sridharan, M. Moerz, J. Hagenauer, D.J. Costello, Analog Rotating Ring De- Figure 2: Same results as in figure but for prediction method B. coder for an LDPC Convolutional Code, in Proc. Inf. Theory Workshop, Paris, France, April 23, p [2] A. Sridharan, D.J. Costello, D. Sridhara, T. Fuja, R.M. Tanner, A Construction for Low Density Parity Check Convolutional Codes Based on Quasi-Cyclic Block Codes, in Proc of IEEE Int. Symp. on Inf. Theory, Lausanne, Switzerland, July 22, p. 48. [3] H.-A. Loeliger, F. Lustenberger, M. Helfenstein, F. Tarköy, Probability and Propagation in Analog VLSI, in IEEE Transactions on Information Theory, vol. 47, pp , Feb. 2. [4] C. Winstead, J. Dai, S. Yu, R. Harrison, C. Myers, C. Schlegel, Analog Decoding of Product Codes, in Proc. of Int. Symp. on Inf. Theory, Lausanne, Switzerland, July 22, p. 23. [5] J. Hagenauer, M. Moerz, A. Schaefer, Analog Decoders and Receivers for High Speed Applications, in Proc. of 22 Int. Zurich Sem. on Broadband Comm., Zurich, Switzerland, Feb. 22, pp [6] S. ten Brink, Convergence behavior of iteratively decoded parallel concatenated codes, in IEEE Transactions on Communications, vol. 49, pp , Oct. 2. [7] D. Mlyinek, Y. Leblebici, Design of VLSI Systems, chapter 4.

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