2017 IEEE 67th Electronic Components and Technology Conference

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1 2017 IEEE 67th Electronic Components and Technology Conference Reliability evaluations on 3D IC Package beyond JEDEC Ganesh Hariharan, Laurene Yip, Raghunandan Chaware, Inderjit Singh, Michael Shen, Kenny Ng, Antai Xu Xilinx, Inc Logic Drive, San Jose CA Abstract 3DIC technology has enabled scaling beyond the Moore s Law to achieve higher transistor count, increased functionality and superior performance. Additionally, this technology allows integrating heterogeneous components such as Processor, FPGA, GPU, Memory, Serdes, etc. on the same interposer die enabling faster computing through reduced latency. The yields on the 3DIC technology have matured and are equivalent monolithic flip chip products. All of the above has made 3DIC technology the key driver for some of the high end computing applications such as Data centers. Any technology is viable only if the end product is reliable and manufacturable with high yields. Understanding the reliability margin of 3D IC package is essential for making them commercially successful. Standard product qualification tests use JEDEC test standards for qualifying the product before ramping into mass production. This might be enough for standard flip chip and wirebond technologies, which have been deployed in the field for many years and the failure modes and acceleration factors are well understood. However, in 3D IC technology, both the assembly process and the assembly materials are new and evolving. Small variations in the process parameters or variations in material concentrations could have significant impact on the reliability. A comprehensive reliability study including component, board and system level is therefore very essential to capture interactions due to process and material variations and material interactions. This paper will compare the results of an extended reliability test evaluation for 3D IC package. This extended reliability study utilized a component level test vehicle, functional board level test vehicle and power cycling test vehicle for comprehensive understanding of the reliability margin. The component level tests followed the standard qualification practice. The functional reliability test set up used specially designed board to test the system level reliability. The functional test vehicle much like a probe card provides access to active circuitry in the stacked silicon, ubumps and C4 bumps while being mounted on the board. This enables replicating the component level tests on a board level. The power cycling tests were performed by utilizing the same functional board test vehicle and special software patterns were implemented to perform power cycling. Special software patterns were designed to heat the device and control the fan for cooling. This study has compared the extended reliability of multiple 3DIC devices with interposer sizes starting from 24mm and extending upto 36mm which is beyond the size of the standard reticle. Also, this study has compared the extended reliability of 3D IC package with eutectic and copper pillar C4 bump. The reliability tests have been conducted on multiple lots over time as an extended reliability monitor to capture process variations. The extended tests have been critical in finding process and material defects critical for improving the overall reliability margin of the 3D IC device. Introduction The demands for increasing functionality and decreasing power to meet the mobility, product miniaturization and integration trends have forced one to look beyond what Moore s law can offer. The 3D IC technology offers excellent platform for achieving superior bandwidth and functionality at much lower power. In this technology, multiple active devices are stacked side by side on an active or passive interposer. The interposer provides a high bandwidth platform for stacked devices to communicate with one another. The integration of various functionally different devices on a high bandwidth interposer helps in maximizing the performance of the device with reduced noise and simplified design. Two prominent methods have been used for assembly of a 3D IC package. In the first method, known as Chip on Chip (CoC), the interposer is fully processed to form TSV and C4 bumps. [2,3] The processed interposer is then assembled on the substrate followed by assembly of the active device. In the second method known as Chip on Wafer on Substrate (CoWoS TM ) the active device is mounted on a full thickness interposer. [4] The interposer is then processed to reveal the TSV s and form C4 bumps. The interposer and top die stack is then assembled on a substrate just like standard flip chip assembly process. The mounting of the active device on a full thickness interposer wafer mitigates the warpage challenges as experienced by the first method resulting in high yielding and a robust assembly process. Copper pillar microbumps are used for accommodating the fine pitch and standoff requirements. The interposer C4 interconnects use standard leaded or lead-free bumps much like a flipchip C4. The presence of various bump interconnects and their associated interfaces offer multitude of reliability challenges. The copper pillar micro bumps by the virtue of their metallurgy, geometry, and size, play a critical role in determining overall device reliability. Studies have reported thermal and thermo-mechanical reliability of the copper pillar micro bumps. [6-11] The results of these investigations show that selecting an appropriate bump metallurgy and surface finish is very important in determining the reliability of a 3D IC package. Also, the 3D IC package encounters multiple thermal regimes during its assembly process. Hence, the polymer materials used in the assembly stack also play a vital role in determining the reliability. Material selection strategies have been presented in various studies for meeting adequate reliability requirements. [2-5] /17 $ IEEE DOI /ECTC

2 Most of the studies reported above have used independent test methodologies to look at each one of these key reliability components. The component level test methodology captures the reliability performance of the microbump and C4 interconnects and its associated interfaces. The board level test methodology covers the BGA solder balls to replicate the effect of board mount assembly process on an end customer s hardware. A special daisy chain substrate is usually designed for the board level testing. With independent test methodologies, the integrated system level reliability of the 3D IC package is not well captured. This is extremely critical in the case of 3D IC packages as both the thin interposer and top die are susceptible to failures from cracks. Studies on both monolithic as well as 3DIC devices have shown the package stiffness and warpage to be the key driver for crack initiation and propagation. Mounting the device on PCB alters the warpage and assembly stiffness significantly. Figure 1: Normalized warpage comparison of an independent 3DIC device and one mounted on board Figure 2: Warpage comparison at room temperature essential to have a unified test vehicle that can capture the warpage effects as well. Results of a unified test vehicle that can test the top FPGA die, inter die interconnections, TSV, C4 bumps and BGA connections while being mounted on a board have been presented in previous version of this study [13]. Also, most of the above accelerated reliability test methods use iso-thermal conditions for accelerated stressing. It is necessary to heat the device by itself and capture the reliability impact to mimic a real end use condition. Various studies have used power cycling test vehicles to mimic real end use scenario. The power cycling test vehicles mostly use a specially designed die with built in thermal resistance heaters. The thermal heaters heat the die using when the device is powered up. While this is a good method to heat the device alone, such test vehicles have their own limitations. These test vehicles often use resistance change to monitor the defects which may not offer the sensitivity that a real product offers. While the test vehicles are good for capturing some massive defects such as C4 bump cracks or delamination however are not good for marginal failures. To capture something like a low-k dielectric crack or single micro bump open, additional test coverage will be required which may not be possible on test vehicle die using dummy silicon. To mitigate this, the power cycling set up in this study has used an existing FPGA device. Self-heating elements capable of heating the active silicon are created to heat the device. Additionally heat sink integrated with a fan is used to actively cool the device to achieve temperature regimen. Since the device under test is an active silicon it can be test for full functionality to catch most of the defects such as underfill delamination, bump cracks, die electric delamination, die crack etc. This paper presents a results of an extensive evaluation on a 3D IC package beyond standard JEDEC framework using component, board and power cycling test vehicles. Also, the reliability challenges for 3D IC devices of different sizes and material sets combinations have been compared. Package Description Multiple 3D IC devices have been used for this study. This includes devices with interposer sizes starting from 24mm and extending up to 36mm which is beyond the size of the standard reticle. The study also compares the effect of C4 bump metallurgy. Both eutectic and copper pillar C4 bump Device Lid TD Gap µbumps Cu pillars TIM Top Die 1 Top Die 2 Figure 3: Warpage comparison at high temperature substrate PTH The warpage of an independent device and one mounted on PCB have been compared in Figure 1-Figure 3. It can observed that warpage behavior of the independent device and one mounted on the board are significantly different. Given the differences in warpage characteristics between an independent device and one mounted on the board it is BGA balls 1518

3 has been used for this study. All devices use a 100um thick interposer. Figure 4: Cross section image of eutectic 3D IC device TD Gap Top Die 2 C4 Bumps ubumps Top Die 3 reduced by carefully optimizing the assembly process and increasing the surface adhesion of underfill and passivation. With above improvements the reliability margin of the copper pillar device enhanced significantly. The copper pillar device passed the extended reliability assessment as well. Organic package substrate Plated Thru Hole (PTH) BGA balls Figure 5: Cross section image of eutectic 3D IC device Parameter Device 1 Device 2 Device 3 Overall 45mm 45mm 55mm Body Size Package 45mm 45mm 55mm Top Chip FPGA Device 7mm 23mm 23.5mm 11.3mm 31.8mm 35.7mm Pitch 45um 40um 40um TSV Interposer Via Diameter 10um 10um 10um C4 Pitch 180um 180um 180um Figure 6: Delamination in copper pillar device Substrate C4 Bump Eutectic Cu Pillar Eutectic Thickness 1.5 mm 1.8 mm 1.8 mm Core 1 mm 1.2 mm 1.2 mm BGA Pitch 1mm 1mm 1mm Table 1: Package description Figure 7: Bump crack in copper pillar device Component level test In component level test the 3D IC device was subjected to accelerated reliability testing both within and beyond JEDEC framework. The device was tested for both temperature cycling and high temperature storage to capture thermomechanical stress induced and material degradation failure modes. To accelerate thermo-mechanical stress the devices were subjected to temperature cycling and high temperature storage stress conditions. The 45mm eutectic device passed both temperature cycling and high temperature storage reliability requirement. The device was further stressed to understand the reliability margin. The 45mm eutectic device showed no signs of weakness even after extended stressing. The 45mm copper pillar device also passed the standard reliability requirement. However the device started showing failures in extended stressing. Failure analysis showed stress induced delamination of C4 underfill and nitride interface leading to bump cracking as illustrated in Figure 5 and Figure 6. To mitigate this, the stress in critical areas was identified using finite element simulation. The package stress was 1519

4 Stress simulation of the 55mm X-Large eutectic device also indicated high stress much like the copper pillar device. The X-Large device also started to fail extended test due to separation between the ubump underfill and passivation. The failures were consistently in the DNP area indicating high stress due to large size of the package. The adhesion strength between underfill and the passivation was enhanced by improving the assembly process. Additionally the stress in the X-Large device was reduced by decoupling the lid from package. The improvements helped X-Large device pass extended reliability. Both improvements helped to mitigate the stress concentration in the interposer and underfill edge. Figure 9: C4 underfill corner crack Figure 8: Delamination in Eutectic device Given the sensitivity of 3D IC technology to material and process conditions it is very important to have an in-depth understanding of the reliability margin. Small process variations could cause small PPM level defects that could impact the reliability margin. While extended reliability is one way to understand the process margin it is not enough. It is very important to sample units from production line at various time frames and stress them to understand process variations and process corners. Continuous reliability monitoring was performed on the both eutectic as well as copper pillar devices. Samples from production lots were subjected to accelerated reliability stressing. Continuous reliability monitoring was effective in identifying failures not captured by standard reliability tests. One such failure mode was corner underfill cracks observed on the opper pillar devices. While units passed electrically physical verification through cross section showed marginal craks starting in the underfill corner for the copper pillar device. [Figure 9] Cross section analysis clearly idicated stress as an inherent factor. While improving the underfill to passivation was helpful in elimiating the delination as highlightled in the previous section, it did not help as much in mitigating the stress in the package. The stress in the C4 underfill corner causing the underfill crack was mitigated through a series of improvements in the processing of the stacked chip on wafer. The interposer dicing process was improved to reduce the stress in the corners. The improvements in the dicing process helped to reduce the stress in the corners significantly. Additionally the underfill process was also improved to ensure consistent underfill fillet. Another process weakness identified by continuous reliability monitoring was C4 bump open. The C4 bump open was more of a time 0 yield issue and the reliability stressing was very effective in exposing the marginal contacts. The primary root cause for these open was the narrow process margin due to high warpage of the 3D IC device. The C4 bump margin was improved by optimizing the reflow process. Reliability monitoring has been continued with all improvements for multiple quarters. No further failures or process weakness have been identified. Board level Test The board level test was conducted using traditional BLR test methods. A special BLR daisy chain substrate and board was designed for this test. The test used a 3.42 mm Megatron 6 board with 28 layers to replicate customer use scenario. The device was thermal cycled from 0 to 100C and the resistance of the daisy chain was continuously monitored. The 45mm eutectic device passed board level reliability studies. The board level performance of the 45mm eutectic device was very comparable to flip chip device of the same size. The 55mm X-large device however showed failures as early as The primary root cause for these failures was the high warpage of the X-large device. The warpage of the device was mitigated by optimizing the lid and lid attach process. With improved lid and lid attach process the board level reliability of the 55mm X-large device improved significantly. The device passed 6000 without any failures as shown in Figure

5 Figure 10: BGA X-Section after 6000 Functional Board Level Test Figure 11: Comprehensive test vehicle set up The functional board level test used a comprehensive test vehicle as described in previous version of this study[13]. The comprehensive test vehicle uses JTAG boundary scan test method to check the device functionality. Test patterns were developed to check the integrity of the active silicon, ubump and C4 interconnects. Functional units mounted on the board were subjected to both high temperature storage (150C) and temperature cycling (0-100C). The failures observed on the component test such as bump cracks were also observed on functional board level tests as well. However, with the improved process the devices passed the 2X requirement for both high temperature storage as well as temperature cycling much like the component test. The improvements for component reliability also helped to enhance the life of the BGA significantly Power In both component and comprehensive test the device is stressed iso-thermally. This is not an exact replication of real use scenario where the device alone sees the higher temperature. The substrate and PCB are always at much lower temperature than the active silicon. To replicate actual use scenario many evaluations have designed a daisy chain silicon with heater networks to heat up the active silicon alone. By actively heating the silicon and placing thermal diodes, studies have been able to replicate a real use scenario. However, such specially designed test vehicles are not as good as the actual product due to their limitations for coverage and sensitivity. The resistance change used for detecting failures are only good enough for identifying gross failures that are more severe. Small failures such as Low K dielectric delamination are not detected by test vehicle. The power cycling evaluation in this study is done using the comprehensive test vehicle on the actual device itself. An external power supply capable of delivering more current is used in conjunction with the comprehensive test vehicle to accommodate the higher current requirement for the power cycling. To achieve higher temperature, self heating elements are created using the logic elements in the FPGA such as LUTS and Flip Flops as described in literature [15]. Toggling the logic circuits at a higher rate increases the dynamic power consumption of the FPGA thereby creating more heat. This methodology is used in this study to power cycle the FPGA. Since the logic elements are distributed evenly across the FPGA, the entire device is heated uniformly. A chain of selfheating elements are generated to increase the toggling rate to achieve higher temperatures at a faster rate. In this study we have used a 10,000 toggling flip flop clocked at 100mhz to achieve 115C on the FPGA device. The device temperature is monitored using the system monitor function. Further the power cycling also requires device to cool down to room temperature. To achieve this a heat sink integrated with fan is used for cooling the device down to room temperature. The fan is controlled using fan controller IP of the FPGA. The fan is set to run at high temperature to accelerate cooling and switch off at room temperature to accelerate heating. During the calibration phase multiple self-heating patterns were tested and peak temperature and time taken to achieve the peak temperature was understood. The fan was programmed to turn on at peak temperature and turn off at room. Also, the heating pattern was design to turn off during Table 2: Results summary the fan operation phase to enable faster cooling. Using this method the device was successfully cycled between 40C and 120C. A sample power cycling profile is illustrated in Figure 12. The eutectic and copper pillar devices were power cycled between 40 and 120C. The devices were tested functionally very 500 to look for ubump cracks, C4 opens and silicon cracks. With the improved process all devices passed No failures were observed Figure 12: Power cycling profile 1521

6 Conclusion The reliability of 3D IC has been studied extensively using component level, board level and power cycling test. The reliability framework was extended beyond standard JEDEC conditions to have a deeper understanding of the reliability margins. Also, parts were sampled from multiple production lots to capture process robustness. The results of this study show that reliability of 3D IC device is very sensitive to assembly process and material selection. 3D IC devices with copper pillar C4 bumps showed some susceptibility to stress induced failures. However, after optimization of the process parameters, design, and with proper material selection all devices passed 2X the JEDEC requirement. The results of the reliability evaluation are summarized in the table below. These results also show that stacked die packages are as robust as standard wirebond and flip chip packages and do not have any issues. Test Compone nt Level Board Level Power Condition Storage Storage 45mm Eutectic mm Cu Pillar mm Eutectic Acknowledgments Authors would like to acknowledge Rich Nakashima for his valuable inputs in developing the test vehicle and Joseph Doan for help with hardware. Also thanks to TSMC BID and QR teams for their excellent support. References 1. K. Saban, Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency 2. R. Chaware, Assembly and Reliability Challenges in 3D Intergration of 28nm FPGA Die on a Large High Density 65nm ive Interposer in Proc. IEEE Electronic Components and Technol. Conf. (ECTC), San Diego, CA, May 29 31, 2012, pp G. Hariharan, Assembly Process Qualification and Reliability Evaluations for Heterogeneous 2.5D FPGA with HiCTE Ceramic in Proc. IEEE Electronic Components and Technol. Conf. (ECTC), Las Vegas, NV, May 28 31, 2013, pp L. Lin, Reliability Characterization of Chip-on-Waferon-Substrate (CoWoS) 3D IC Integration Technology in Proc. IEEE Electronic Components and Technol. Conf. (ECTC), Las Vegas, NV, May 28 31, 2013, pp B. Banijamali, Reliability Evaluation of a CoWoSenabled 3D IC Package in Proc. IEEE Electronic Components and Technol. Conf. (ECTC), Las Vegas, NV, May 28 31, 2013, pp J.F.Li, Interfacial reaction in Cu/Sn/Cu system during the transient liquid phase soldering process in Proc. Acta Materialia, Volume 59, Issue 3, February 2011, Pages Y.Wang, Effect of Intermetallic Formation on Electromigration Reliability of TSV Microbump Joints in 3D Interconnects in Proc. IEEE Electronic Components and Technol. Conf. (ECTC), San Diego, CA, May 29 31, 2012, pp T.H.Lin, Electromigration Study of Micro Bumps at Si/Si Interface in 3DIC Package for 28nm Technology 9. and Beyond in Proc. IEEE Electronic Components and Technol. Conf. (ECTC), Lake Buena Vista, FL, May 31 June 3, 2011, pp Y.C.Liang, Side Wall Wetting Induced Void Formation due to Small Solder Volume in Microbumps of Ni/SnAg/Ni upon Reflow in Proc. ECS Solid State Lett. 2012, Volume 1, Issue 4, Pages P60-P H.Liu, Effect of IMC Growth on thermal cycling reliability of micro solder bumps in Proc. IEEE 15th Electronics Packaging Technology Conference, 2013, Pages P D.Mark, Localizing Open Interconnect Defects using Targeted Routing in FPGA s in Proc. ITC INTERNATIONAL TEST CONFERENCE, 2004, pp G.Hariharan, A Comprehensive Reliability Study on a CoWoS 3D IC Package in Proc. IEEE Electronic Components and Technol. Conf. (ECTC), San Diego, CA, May 28 31, 2013, pp L.Yip, Board Level Reliability Optimization for 3D IC Packages with Extra Large Interposer in Proc. IEEE Electronic Components and Technol. Conf. (ECTC), Orlando, FL, May 28 31, A.Amouri, Self-Heating Thermal-Aware Testing of FPGAs, in Proc. IEEE 32nd VLSI Test Symposium (VTS), Napa, CA, April 13-17,

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