# Estimators Also Need Shared Values to Grow Together

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3 TECHNICAL REPORT TR11-04, COMNET, TECHNION, ISRAEL 3 Fig. 1. CEDAR structure. The flow pointers on the left point to shared estimators on the right. For example, the estimator for flow F 0 is A 1 = 1.2 of bits can be converted easily into a CEDAR structure with asymptotically negligible effect on the estimation error. This applies for instance to the SAC [20] and DISCO [21] counter estimation methods. Theorem 1: Any counter estimation method using a fixed number of bits per counter estimate can be converted into the CEDAR structure with the same estimation error, and an asymptotically negligible overhead as N. Proof: Consider an estimation method that uses q bits per counter for counter estimation. Thus, it can have a maximum of 2 q distinct symbols. If we build from these symbols an estimation array of size L = 2 q, then we can use the counter symbols as pointers into this estimator array and run the original algorithm without any change. Therefore we get a CEDAR structure that keeps the same estimation error. In addition the structure overhead is the additional contribution of the estimator array, i.e. q 2q N q = 2q N N 0. C. Performance Measures In the paper we only use unit increments that represent packet arrivals. Note that the estimation error with variable increments (e.g. when measuring bytes) is actually lower given the same scale, because it enables more precise scale jumps, and therefore using unit increments results in a worst-case analysis. We denote by T (l) the random variable that represents the required amount of traffic for a certain flow to point to estimator A l, i.e. its hitting time. As in [20], [21], assuming our algorithms yield unbiased estimators and assuming E[T (l)] = A l, we will define the relative error (or coefficient of variation) as Var[T (l)] σ[t (l)] δ[t (l)] = 2 = (E[T (l)]) E[T (l)] D. Static CEDAR Algorithm We start by introducing the static version of CEDAR, which uses a static and pre-determined estimator array A. Later, in Fig. 2. Update mechanism of the CEDAR algorithm given consecutive packet arrivals for a given flow. The flow counter estimate is initialized at A 0 = 0. After the first arrival, the difference between A 0 and A 1 is 1, therefore the update step is deterministic with probability p = 1/1 = 1 and the new estimate is A 1 = 1. After the second arrival, A 2 A 1 = 3, therefore the flow pointer is incremented with probability 1/3 to A 2 = 4. At the third arrival, A 3 A 2 = 5, therefore the increment probability is 1/5. Here it is not incremented. Section IV, we will introduce the dynamic version of CEDAR that enables scaling the estimator array. In the static CEDAR algorithm, we make two simplifying assumptions on the fixed CEDAR structure. First, we assume that the estimator values A i are defined in ascending order, with A 0 = 0. We denote the differences between two successive estimators as D i = A i+1 A i, where 0 i L 2, and further assume that D i 1 for any i. For instance, in Figure 1, D 0 = = 1.2 and D 1 = = 2.5. As The static CEDAR algorithm works as follows. At the start, all flow counters point to A 0 = 0. Then, at each arrival of a packet from flow j, which corresponds to a unit increment of its real counter value, the flow s pointer F j is incremented 1 1 by one with probability D Fj = A Fj +1 A Fj. In other words, if the flow pointer first points to estimated value A i, then it either starts pointing to A i+1 with probability 1/D Fj, or continues pointing to A i with probability 1 1/D Fj. Note that since D i 1 for any i, these probabilities are well defined. Figure 2 further illustrates an example of such update sequence in the static CEDAR algorithm. E. Unbiasedness and Traffic Expectation Given our definition of the static CEDAR algorithm, we first show that the expectation of random variable T (l) equals the estimated value A l. This means that the expected hitting time of A l is exactly A l, i.e. the expected number of arrivals needed to reach some estimated value is exactly this estimated value. Theorem 2: The hitting time T (l) of estimator A l satisfies the following property: E[T (l)] = A l Proof: We can divide T (l) into l i.i.d geometric random variables G(p i ) with parameter p i = 1 D i, i = [0,..., l 1], therefore [ l 1 ] E[T (l)] = E G( 1 [ ) = E G( 1 ] ) = D i = A l D i D i In addition, regardless of the exact values used within estimation array A, the CEDAR estimation is unbiased, as long as we assume that the estimation scale is unbounded (or

4 TECHNICAL REPORT TR11-04, COMNET, TECHNION, ISRAEL 4 that its maximum is never reached). The unbiasedness proof of CEDAR is similar to the proof of Theorem 1 in DISCO [21], therefore we do not repeat it. Property 1: CEDAR estimators are unbiased. III. RELATIVE ERROR MINIMIZATION A. Min-Max Relative Error A network device designer will want to obtain a guarantee that the counter estimates have good performance no matter how large the counters are. For instance, such a guarantee might be that the relative error is below 5% over the whole scale of counters. Unlike former approaches that restrict the counter estimators to specific values, the flexibility of the CEDAR structure enables us to analytically determine and implement the optimal estimation array that achieves such a guarantee. In the remainder of this section, we first determine the values of this optimal estimation array in Theorem 3, then prove that it is indeed optimal in Theorem 4. More specifically, given an estimation array size L and a fixed maximal estimator value A L 1, we want to determine the set of estimator values {A 0,..., A L 1 } that minimizes the maximum relative error over all estimators, i.e. achieves min A max l δ[t (l)]. In other words, this set should minimize the guaranteed error δ such that for all l, δ[t (l)] δ. As we saw in Theorem 2, T (l) is a sum of l i.i.d geometric random variables, therefore δ[t (l)] = Var[T (l)] (E[T (l)]) 2 = and we can rewrite δ[t (l)] δ for all l as l : F l (D 0,..., D l ) = l 1 1 1/D i 1/Di ) 2 2 ( D i ( l ( ) l ) 2 D 2 i D i δ 2 D i 0 (1) We later show in Theorem 4 that in order to achieve such min-max relative error, all estimators must reach an equal relative error δ, that is, l : δ[t (l)] = δ, which we can rewrite as l : F l (D 0,..., D l ) = 0. We first prove in the following theorem that we achieve such an equalrelative-error estimation array iff the estimation values are given by the following recursive equation, D l = 1 + 2δ2 l 1 D i 1 δ 2, (2) with D 0 = 1 1 δ 2, before proving in Theorem 4 that we indeed need to achieve this equal-relative-error to provide an optimal guarantee. Theorem 3: Given a target relative error δ, and the L 1 constraints: l [0, L 2], F l = 0, then the estimation value increments D l are necessarily given by the recursive function in Equation (2). Proof: First, we highlight the recursive nature of the F l functions. Extracting D l from F l yields: F l = Di 2 + Dl 2 D i D l ( ) ( D i ) 2 + 2D l D i + Dl 2 =(1 δ 2 )Dl 2 (2δ 2 D i + 1)D l + Di 2 D i ( Di 2 ) 2 δ 2 = 0 (3) } {{ } F l 1 Assigning F l 1 = 0 immediately gives Equation (2). The following theorem proves that minimizing the maximal relative error δ for a given A L 1 is equivalent to maximizing A L 1 for a given maximal relative error δ. More significantly, it demonstrates that both are equivalent to equalizing all relative errors, therefore yielding the recursive equation obtained above (Theorem 3). Theorem 4: Given the L 1 constraints: l [0, L 2], F l 0, the following claims are equivalent: (i) A L 1 = L 2 D i is maximal (maximizing A L 1 ). (ii) l [0, L 2], F l = 0 (equalizing all relative errors). (iii) δ is the minimal guaranteed relative error (minimizing δ). Proof: We start by proving that (i) (ii). Assuming L 2 D i is maximal, the (L 1) th equality, F L 2 = 0, is given by the following lemma: Lemma 1: Assume that l [0, L 2], F l 0. If A L 1 = L 2 D i is maximal then F L 2 = 0 Proof: We assume by contradiction that there is a set {D 0,..., D L 2 } that satisfies all L 1 constraints and achieves maximal L 2 D i but F L 2 < 0. We choose ɛ > 0 such that ( ) ɛ < min 1, F L 2 L 2 D2 i 2D L 2 We increase D L 2 by ɛ and thus increase the maximal sum L 2 D i by ɛ. Changing D L 2 has no effect on the other L 2 constraints F l 0, l = 0,..., L 3. Consider now the (L 1) th constraint: F L 2 (D 0,..., D L 2 + ɛ) = L 3 D2 i + (D L 2 + ɛ) 2 L 2 D i ɛ L 2 D2 i L 2 D i ( L 2 δ 2 ( L 2 D i + ɛ) 2 < D + ɛ2 ɛ + 2ɛD L 2 i) 2 ( L 2 D < i) 2 F L 2 (D 0,..., D L 2 ) + 2ɛD L 2 ( L 2 D i) 2 < 0 (4) We now prove that F L 2 = 0 F L 3 = 0, and more generally, by induction, F l = 0 F l 1 = 0, i.e. F l = 0 for all l. We assume by contradiction that F L 3 < 0 and show that this leads to D i = D j for all i, j, but assigning identical

6 TECHNICAL REPORT TR11-04, COMNET, TECHNION, ISRAEL 6 in this case we are in option 2 and the maximum is attained on the ellipse tangent at P 2 where x l = y l, i.e., when D l = D l+1. The following lemma proves this formally for all recursion cycles: Lemma 2: Under the constraint: L 3 k F = (1 δ 2 )x 2 (1 + 2δ 2 D i )x (2kδ 2 )xy L 3 k + k(1 kδ 2 )y 2 k(1 + 2δ 2 D i )y + F L 3 k = 0 (k is a positive integer, F L 3 k 0). The expression x+ky is either unbounded or attains its maximum when x = y. Proof: We can see that F (x, y) is a continuously differentiable function and x + ky is affine (On KKT s sufficient conditions see [25]). Therefore we can use Lagrange multipliers to find the extremum of x + ky under the constraint. Note that (x + ky)/ x = 1 and (x + ky)/ y = k. L 3 k F x = 2kδ2 y + 2(1 δ 2 )x (1 + 2δ 2 D i ) = 1 λ L 3 k F y = 2k(1 kδ2 )y 2kδ 2 x k(1 + 2δ 2 D i ) = k λ eliminating λ by equating F y = k F x, we get: 2kx = 2ky. That is, the extremum M of x + ky under the constraint F is achieved when x = y. Furthermore, let us denote by x M the value of x (which is also the value of y) where M is attained, the derivative d(x + ky)/dx is positive in the domain 0 x x M. This is easily shown by the fact that dy/dx = F L 2/ x F L 2 / y = 1/k at x = x M. At x = 0, dy/dx > 0 (assign x = 0 and y > 0 at the partial derivative equations) and therefore, since F is convex,d(x + ky)/dx 1 + k( 1/k) = 0 when 0 x x M. That is, (x + ky) is an increasing function at the domain 0 x x M, attaining its maximum at x M. Thus, if x + ky under the constraint F has a maximum M (e.g., when the quadratic curve F is an ellipse), M is attained when x = y. In case the quadratic curve F is unbounded (a hyperbola or parabola) then x + ky does not have a maximum under the constraint F. Note that the private case of the lemma when k = 1 is the case we just explored in Equation (5), where F L 2 = 0 is the constraint. For this case, the maximum induced by the constraint is (by assigning x = y and solving Equation (6)): x M L 3 = 2C 1 + 4C 2 1 4(2A + B)F L 4 2(2A + B) Now, if x M L 3 x0 L 3 (option 1), then the maximum of x + y (and therefore the maximum of L 2 D i) is attained at (8) (9) x 0 L 3, i.e., when F L 3 = 0. Also note that if F L 4 = 0, then x M L 3 x0 L 3 since C 1/A < 2C 1 /(2A + B). By our contradiction assumption, F L 3 < 0, the maximum must be attained when x M L 3 < x0 L 3 and F L 4 < 0. Therefore, F L 3 < 0 F L 4 < 0. By Lemma 2, the maximum must be attained when x = y, i.e., when D L 3 = D L 2. This proves item (1) of the recursion steps for the first cycle. Now, we can continue to the next recursion step l = L 4. We can plug-in D L 3 = D L 2 = D into F L 2 = 0 and get the following constraint in x l = D L 4 and y l = D L 3 = D L 2 = D: L 5 F = (1 δ 2 )x 2 l (1 + 2δ 2 D i )x l (4δ 2 )x l y l L 5 + 2(1 2δ 2 )yl 2 2(1 + 2δ 2 D i )y l + F L 5 = 0, (10) which is a private case for k = 2 of Lemma 2. Applying the lemma onto the new constraint, we get that the maximal value of x l + 2y l on F is attained when x l = y l. In a similar manner to what was done above, we can formulate x 0 L 4, which is achieved when F L 4 = 0 and x M L 4, which is achieved when x l = y l (i.e., when D L 4 = D L 3 = D L 2 = D). Again, if x M L 4 x0 L 4, then the maximum of x l + 2y l (and therefore the maximum of L 2 D i) is attained at x 0 L 4, i.e., when F L 4 = 0. But, this will mean that (in the level above) x M L 3 x0 L 3, which violates our contradiction assumption. Thus, the maximum must be attained when x M L 4 < x0 L 4 and F L 5 < 0. By the lemma, it is therefore attained when x l = y l, i.e., when D L 4 = D L 3 = D L 2 = D. Applying the same logic recursively for k = 3,..., L 3 we will get that in order not to violate the contradiction assumption, the maximum is attained when D 0 = D 1 =... = D L 2. However, this is definitely wrong since from F 0 it is easy to see that D 0 1/(1 δ 2 ), and we can easily find a value that satisfies the constraints and is greater than (L 1)/(1 δ 2 ) (for example, the one derived from Equation (2) for δ 2 > 0). This proves that for the maximal A L 1 = L 2 D i we must have F L 2 = 0 and F L 3 = 0. We can continue inductively by assuming F k = 0 for k = L 3,..., 1 and proving in the same way that F k 1 = 0. We prove now that (ii) (i). Assuming for all l F l (D 0,..., D l ) = 0, we get the recursive formula from Equation (2). This formula defines L 1 linear equations that can be represented as a triangular matrix, i.e. they are linearly independent. This means there exists a solution and it is unique. Now we show that (iii) (i). Denote by M = A L 1 the maximal value of L 2 D i for a given δ. Equation (2) defines a function M(δ) = L 2 D i(δ). It is easy to see from Equation (2) that M(δ) is a strictly increasing function of δ (since the D l s increase as δ increases). Therefore, there exists an inverse function δ(m), which for any given value A L 1, returns δ such that M(δ) = A L 1. This is the minimal δ since a smaller δ will not satisfy the relative error constraints, whereas a larger δ will not be minimal.

7 TECHNICAL REPORT TR11-04, COMNET, TECHNION, ISRAEL 7 In practice, we start with the best estimation array that matches an initial maximal relative error δ 0, i.e. the estimation array with the largest maximal estimator. This estimation array is unique, as we proved in Theorem 4. As more and more packets are streaming in and the maximal flow counter is going to exceed our maximal estimation value, we set a new relative error of δ new = δ 0 + δ step and build a new matching estimation array. We further proceed in the same way for the next iterations. Fig. 4. The minimal max-relative-error, δ, vs. maximal estimator value, A L 1, for several bit widths, log(l) Fig. 5. CEDAR scaling - A is a CEDAR estimation array that matches a relative error δ 0. A is a CEDAR array that matches a relative error δ 0 +δ step, therefore it has an higher maximal value. Each flow pointer that points to an estimator in A is converted to one of the two closest estimators in A, according to probability p. B. Capacity Region of Static CEDAR Figure 4 illustrates the maximal possible guaranteed region for CEDAR, as provided by the min-max optimization. It plots the maximal estimator value as a function of the min-max relative-error, given several possible bit widths, as indicated in Equation (2). For instance, given log 2 L = 10 bits, i.e. L = 2 10 = 1024 estimators, we can achieve a min-max relative error of δ = 5% using a maximal estimator value of A L 1 = , and an error of δ = 10% using A L 1 = Alternatively, each plot also defines the lowest possible relative error guarantee given a counter scale, as proved in Theorem 4. For instance, given A L 1 = , it is not possible to provide a better guarantee than δ = 5%. Figure 4 also shows how an increase in the number of bits, i.e. in the available memory resources, leads to an increase in the maximal counter value and/or a decrease in the guaranteed relative error. A. Motivation IV. DYNAMIC UP-SCALE We now introduce the full CEDAR algorithm that can dynamically adjust to the counter scale. This algorithm is used to support an unlimited counter value, yet also provide a good relative error at any given time. The strength of our algorithm is the fact that we control the up-scaling by adjusting the relative error rather than changing the maximal estimation value. In this way the error of the entire counter scale is always under control and can be fine tuned by the user. B. Algorithm In order to support up-scaling we use two estimation arrays A and A in a simple ping-pong way. We initialize A with equal-error estimators that match an initial error of δ 0 according to Equation 2, and likewise initialize A with estimators that match δ 0 + δ step. Therefore A has an higher maximal estimation value than A. We start by using the static CEDAR algorithm with the A array. Once the maximal flow pointer is getting close to the end of A array such that max j (F j ) i threshold, where i threshold is an arbitrary threshold value, we perform the following upscale procedure: For j=0 to N 1 do 1) Set l = F j 2) Find m such that A m A l < A m+1 (e.g. using binary search within A ) 3) Set p = A l A m A m+1 A m 4) Set F j = m + 1 with probability p and F j = m with probability 1 p Figure 5 depicts a single step of the up-scale procedure. We run the up-scaling procedure in parallel with the realtime counter updates, i.e. without stopping the CEDAR update algorithm. We use the current-flow index f as follows: assuming a new packet arrival for flow F i, if i < f we use the new estimation array A, and otherwise use A (since current flow f has not been up-scaled yet). When the up-scaling procedure ends, we prepare A for the next up-scaling event by filling it with new estimation values that match a new error of additional δ step, i.e. after a new upscaling event the relative error is δ 0 +2 δ step and after n events it is δ 0 + n δ step. C. CEDAR Up-Scale Unbiasedness In the following theorem we show the unbiasedness of CEDAR up-scale algorithm. Since we know from the unbiasedness of static CEDAR that estimation updates are unbiased as long as the scale is maintained, the proof essentially shows that up-scaling does not introduce bias. As for static CEDAR, the result assumes that either the estimator scale is unbounded, or up-scaling is done such that the maximum estimator value is never reached. Theorem 5: The CEDAR up-scaled estimators are unbiased. Proof: In the up-scaling phase, let C denote the real number of packets for the flow, Ĉ its estimation under the old scale, and Ĉ its estimation (Ĉ ) under) the new scale. Then we need to show that E = E (Ĉ = C. Using the law

8 TECHNICAL REPORT TR11-04, COMNET, TECHNION, ISRAEL 8 [Ĉ ] (Ĉ ) of iterated expectation E = E Ĉ, it is therefore (Ĉ ) sufficient to show that E Ĉ = Ĉ. Consider now a random path of the counter estimator. As illustrated in Figure 5, denote by A l the random variable that represents the estimation value before the up-scaling. Also define A m on the new scale such that A l [A m, A (Ĉ m+1). Then ) we just need to show that for any such A l, E Ĉ = A l = A l. Denote a Bernoulli random variable with parameter p as B(p). Then we obtain: (Ĉ ) ( E Ĉ = A l = E A m + (A m+1 A m) ( A B l A ) ) m A m+1 A m = A m + (A m+1 A A l m) A m A m+1 A m = A l we can see again, CEDAR max relative error is better by third from both SAC and DISCO. Interestingly, we can see how SAC estimator restriction to the form a2 b causes high oscillations in its relative error. In order to check the error adaptation of the CEDAR up-scaling algorithm, we ran again trace [26] using 12-bit estimators but this time we stop the stream at three different points: after 1% of the trace, 10% and 100%. At every point we sample the counter estimations through the entire counter scale and measure the relative error. We compare the results to a static CEDAR, i.e. a CEDAR array that uses no upscaling and relies on the maximal counter value from the beginning. Figure 8 shows the relative error results. We can see in Figure 8(a) that without the scaling algorithm the error is always 3% no matter what the real maximal counter value is. When using scaling, like in Figures 8(b) and 8(c), we can see that the error is adjusted to the current maximal counter (after 1% and 10% of the trace). V. CEDAR EVALUATION We evaluate the performance of CEDAR on real Internet packet traces ( [26] and [27]). First, we verify the unbiasedness of the CEDAR estimator, and also check that its relative error is constant over the entire counter scale, as proved in Theorem 4. In Figure 6 we show the CEDAR estimation results with a 4KB estimation array (12-bit estimators). The initial scale is set to a relative error of δ 0 = 1% with steps of δ step = 0.5%. The maximal value we reached is 10 6 which is equivalent to an error of 3%. As it shown in the figure, CEDAR keeps its unbiasedness over the entire scale as well as its relative error. In Figure 7 we compare the CEDAR relative error to SAC and DISCO with two different Internet traces. In Figures 7(a) and 7(b) we are using 12-bit estimators. CEDAR parameters are just the same as the previous experiment. For SAC we used a 8:4 bit allocation as recommended in [20], that is, 8 bits to the magnitude (which is denoted in [20] by A[i]) and 4 bits to the exponent (denoted by mode[i]). As DISCO introduces no up-scaling scheme we need to make some assumption on the maximal estimated value in order to compare it to SAC and CEDAR, we assume it can scale up to 32-bit counter. Therefore, we set the DISCO exponent parameter to b = which can reach the maximum real counter limit with no need to do up-scaling. As shown in the figure SAC achieves the best error in small counter values, since for small values it can represent the exact counter value. However, from counter value of 10 3 and on we see that it performs the worst, reaching a relative error of above 5%. Regarding DISCO, it performs better than SAC, however it is bounded between 4% and 5%. As we can see, CEDAR keeps a near-constant relative error throughout the whole counter scale in spite of the fact that it performed 4 scaling steps. CEDAR relative error is better by third from that of DISCO and SAC. In Figure 7(c) we use trace [27] again but with 8-bit estimators. For CEDAR we use again δ 0 = 1% and δ step = 0.5%, for SAC we use a 5:3 bit allocation and for DISCO we use an exponent parameter of b = As VI. FPGA IMPLEMENTATION A. Implementation Description In this section we examine CEDAR implementation using Xilinx Virtex-5 FPGA. We use 192KB RAM for the flow pointer array and 16KB for the estimation array. Each estimator is 32 bit width. The estimation values (given by Equation( 2)) are multiplied by 1000 in order to avoid float operations, yet keep a reasonable accuracy. The maximal design clock rate is 170MHz, therefore, assuming packets are accessed through a 32-bit bus with the same clock, our design may support streams of up to 5.4Gbps. Without any optimization our design uses x6 LUT and 2500 flip-flops (roughly equivalent to 12K gates on ASIC design). In order to enable fast reading and writing operations we use DPR (Dual Port RAM) for all arrays, in this way both the CEDAR module and the client application can access any array at any time. The CEDAR module has an I/O register interface in order to program it with initial configurations, e.g. array sizes, and commands, e.g. start/stop. Figure 9 depicts our implementation block scheme. The CEDAR module itself is built of a simple state machine. For any incoming packet we first fetch the flow pointer, then we fetch the two successive estimators and finally we decide whether to update or not the flow pointer. Both the flow pointer array and the estimation array are stored in a dual-port RAM in order to enable the client application fast reading of the flow counter estimation at any given time. A second estimation RAM is drawn with a dashed line in order to support the up-scaling algorithm. The up-scaling algorithm is done by a dedicated SW application. In order to trigger this application, CEDAR generates an interrupt when the maximal flow index exceeds a programmable threshold. In addition, CEDAR has a current-up-scaled-flow-index register. This register is updated by the up-scaling application during its iteration through the flow pointer array. CEDAR uses this register in two manners: to decide which estimation array should be used for a specific flow (by comparing the flow pointer to that register) and to lock the updating of the current up-scaled flow.

9 TECHNICAL REPORT TR11-04, COMNET, TECHNION, ISRAEL 9 (a) CEDAR unbiased estimation vs. real counter values (Property 1) (b) CEDAR constant relative error (Theorems 3 and 4) Fig. 6. CEDAR results on a a real IP packet trace [26] using 12-bit estimators (a) Trace [26] counter estimation using 12-bit estimators (b) Trace [27] counter estimation using 12-bit estimators (c) Trace [27] counter estimation using 8- bit estimators Fig. 7. Relative error comparison on real IP packet traces [26] and [27] using 12-bit and 8-bit estimators (a) CEDAR without scaling for 12-bit estimators. The maximal value is aimed at The matching relative error is kept at 3% throughout the trace (b) CEDAR with scaling for 12-bit estimators. The relative error is adjusted according to the current maximal counter value (c) CEDAR with scaling for 8-bit estimators. The relative error is adjusted according to the current maximal counter value Fig. 8. Relative error comparison between non-scaling CEDAR to a scaling CEDAR using trace [26] and sometimes even 4: one reading of the flow pointer, two readings of successive estimators and an optional writing of a new flow pointer. In our implementation we handle each packet separately. That is, we do not accept the next packet till we finish a full cycle of the CEDAR state machine. This imposes a delay between 2 successive incoming packets of at least 4 cycles. Typically, this is not a real problem since the packet minimal size is bounded by its header size which is usually longer than 4 words. So assuming we have a word access per cycle, our 4-cycle delay will not cause any stream halt. Fig. 9. CEDAR FPGA implementation block scheme - CEDAR is implemented as three states SM. We use DPR (Dual Port RAM) for estimator array and for flow pointers. Thus, both CEDAR module and application can access arrays to perform fast updating and fast reading B. Performance Analysis We would like now to analyze the proposed model performance. As shown in the figure, we have 3 RAM accesses To conclude, we get a simple implementation which can work with high stream bit-rates and enable fast reading by the client application. Assuming an ASIC solution is much faster than FPGA, our implementation can probably support up to tens of Gbps. In terms of size, our implementation requires in the worst case 12K Gates, which is negligible comparing to the flow pointer RAM requirement.

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