IEEE Circuits and Systems Society (CASS) HELLENIC OPEN UNIVERSITY. Multi-Modal Learning Course on Digital Systems Design Using VHDL & FPGAs

Transcription

1 IEEE Circuits and Systems Society (CASS) HELLENIC OPEN UNIVERSITY Multi-Modal Learning Course on Digital Systems Design Using VHDL & FPGAs

2 Contents Contents... 2 A brief description of the workshop... 3 Appendix A: Course schedule & Virtual classrooms... 5 Appendix B: Workshop participants... 6 Appendix C: Sample attendance certificate... 7 Appendix D: Virtual classroom screen snapshot... 8 Appendix E: The system: hardware and web-gui/ide... 9 Appendix F: Final examination snapshots Appendix F: Course announcements& Leaflets... 13

3 A brief description of the workshop The IEEE Circuits and Systems Society (CASS) Greece Chapter ( ) under the sponsorship of an IEEE Circuits and Systems Society grant, organised an intensive multimodal learning course including tutorials and workshops on digital systems design using VHDL and FPGA boards on a remote laboratory facility as well as a visit to a microelectronics business incubator. The workshop was implemented in co-operation with the Digital Systems and Media Computing Laboratory (DSMC of the School of Science and Technology of the Hellenic Open University (HOU), and targeted at IEEE student members. Assistant Professor Theofanis Orphanoudakis (DSMC lab director) carried out the tutoring activities and coordinated the running of the workshop, while prof. Athanassios Skodras founder of the DSMC lab, currently professor at the University of Patras and Chair of the Greece IEEE Section and past-chair of the Greek Chapter of IEEE CASS) assisted in the overall coordination and the planning of the social events and visits and Dr. Vassilis Fotopoulos and Anastassios Fanariotis assisted in setting up the hardware infrastructure and remote access application. The workshop was implemented on a blended learning basis: it consisted of lectures and laboratory exercises carried out at a distance, according to the standard tutoring practice of HOU. The lectures were delivered via virtual classroom infrastructure and the laboratory exercises were carried out remotely. Students were registering to a website and then connected to one of four installed systems. Code was written, compiled locally using the VHDL design suite provided by ALTERA and uploaded through the web interface supporting interaction with the lab infrastructure and results of running the code in the real systems were visualized by means of a web camera. The systems were up and running 24/7. The aim of the workshop was to introduce participants to digital design using VHDL and to allow them to practice by using state of the art EDA tools (Altera Quartus, Modelsim) and accessing a fully functional remote lab that includes FPGA boards and pre-connected peripheral hardware. Students were able to experiment with existing hardware and design their own digital systems using the ALTERA DE0-nano board, several, sensors, servo motors, displays and LEDs. The range of exercises covered the full series of exercises that a student in a conventional on-site lab has to experiment with during a typical university term. The duration of the workshop was 5 weeks. Four virtual lectures (1 per week) were delivered, while students sat a final laboratory examination at DSMC premises, in Patras. HOU prepared an attendance certificate, bearing the logos of IEEE CASS and DSMC issued to all students who fulfilled all requirements, namely: - Attendance of all lectures, - Successful completion of 3 weekly assignments, - Successful completion of the final hands-on examination (physical presence was required). Twenty one (21) students, six (6) females and fifteen (15) males, participated in the workshop. Fifteen of them accomplished all assignments and made it to the final exam,

4 while six dropped out due to other engagements since the schedule was strict and time was short. The students are with the National Technical University of Athens, the University of Central Greece, the Hellenic Open University, the Technical University of Thrace (Democritus University of Thrace) and the University of Patras. They are located in different cities of Greece, in distances ranging from 200 km to 750 km away from Patras, where DSMC is situated. All students received the educational material for the workshop electronically. Actually the whole communication except from the lectures (which were conducted with Centra) was carried out through a learning management system hosted by which proved to be very efficient and much more appealing comparing to classic well known LMS facilitating the use of a content management system, posting announcements and using the electronic Forum for discussions, the scheduling of events, lectures and assignments, tracking students progress etc. Each lecture aimed at: - Disseminating specialized knowledge to the students, - Discussing issues arising while studying the material The study plan was prepared with an estimation of dedicating 15 hours of study per week (studying the material, completing the exercises, attending the lectures). All exercises were evaluated by the tutor and sent back to the students, along with a solution (including their score and comments on their work). The study material consisted of: - Access to an e-book (available in Greek only) - One set of slides per lecture - Intermediate and final project descriptions - Supplementary electronic material and datasheets - Free educational software (namely Altera Quartus II including Altera-Modelsim) as well as open source VHDL simulation tools (ghdl, edaplayground/epwave)

5 Appendix A: Course schedule & Virtual classrooms Week # Date of class Date of exercise due Subject of class 0 November 11 - Introduction & VHDL part I 1 November 18 November 25 Mid-term project VHDL part II & simulation tools 2 December 25 - FPGA programming tools and Lab environment 3 December 2 December 9 Final project Advanced examples Final exam (with physical presence at DSMC premises): December 14. Visit to the Corralia mi-cluster -Nano/Microelectronics-based Systems and Applications Cluster: December 15

6 Appendix B: Workshop participants Surname Name IEEE # 1 Δημητρόπουλος Μάρκος mdimitropo@ceid.upatras.gr - 2 Ζαννεττής Χρυσόστομος ece7691@upnet.gr - 3 Κονδύλη Γαλήνη galini_kon@hotmail.com Κουρής Αλέξανδρος kouris@ceid.upatras.gr Συνοδινός Άρης asynodin@mech.upatras.gr Ζαχείλας Ιωάννης gianniszhs2013@gmail.com Ζυγάς Κωνσταντίνος zygas@ceid.upatras.gr Καλαμπούκας Ανδρέας icsd09042@icsd.aegean.gr Μάλαμας Δημήτρης dmalamas@gmail.com Μαράκας Ευθύμιος mmarakas@gmail.com - 11 Μουστάκας Παναγιώτης panos_mous_93@hotmail.com Μουτσούρη Ειρήνη imoutsouri@gmail.com Μπερνιδάκη Δήμητρα ece7851@upnet.gr Ντάγιου Ευριδίκη evrithess@gmail.com - 15 Ντούκας Μιχαήλ ece7867@upnet.gr Παναγοπούλου Δάφνη-Ελένη daphnee21@gmail.com - 17 Παπαδόπουλος Μάριος spiderman@hol.gr - 18 Ρέτση Βασιλική retsi@ceid.upatras.gr - 19 Τσαλαπάτης Αιμίλιος aimilios.tsalapatis@gmail.com Τσαμπουράς Δημήτρης dimitris.tsampouras@hotmail.com - 21 Ψιακής Ραφαήλ ece6893@upnet.gr -

7 Appendix C: Sample attendance certificate

8 Appendix D: Virtual classroom screen snapshot Participants Tutor Slides or shared application windows Annotations

9 Appendix E: The system: hardware and web-gui/ide The two systems installed at the labs, working 24/7 The hardware setup and system architecture

10 The web based gui & ide.

11 Appendix F: Final examination snapshots Two snapshots of the final examination are presented below

12 followed by a snapshot of of the visit to the π1 innohub of Patras

13 Appendix F: Course announcements& Leaflets