A 1.25-GHz 0.35-m Monolithic CMOS PLL Based on a Multiphase Ring Oscillator

Transcription

1 910 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 6, JUNE 2001 A 1.25-GHz 0.35-m Monolithic CMOS PLL Based on a Multiphase Ring Oscillator Lizhong Sun and Tadeusz A. Kwasniewski, Member, IEEE Abstract A general ring oscillator topology for multiphase outputs is presented and analyzed. The topology uses the interpolating inverter stages to construct fast subfeedback loops for long chain rings to obtain both multiphase outputs and higher speed operation. There exists an optimum number of inverter stages inside a subfeedback loop which gives the highest oscillation frequency. A fully integrated 1.25-GHz m CMOS phase-locked-loop clock generator that incorporates the proposed voltage-controlled oscillator topology was designed and implemented for a data transceiver. It provides eight-phase outputs and achieves RMS tracking jitter of 11 ps from a 3.3-V power supply. Index Terms Analog integrated circuits, clock generation, frequency synthesizer, phase-locked loop. Fig. 1. Simplified block diagram of a data transceiver. I. INTRODUCTION THE phenomenal growth in information transport has created greater demand for very high-speed integrated circuits. Important components for the high-capacity networks include transceivers which incorporate clock generators, clock/data recovery circuits (CDR), multiplexers (MUX)/demultiplexers (DMUX) and I/O buffers. Fig. 1 shows the simplified block diagram of a data transceiver. In the transmitter, the MUX converts the internal byte-wide (parallel) data stream to a bit serial stream and drives a high-speed output buffer. In the receiver, the clock recovery circuit regenerates the clock and defines the best time to sample the data in terms of the received signal-to-noise ratio. Data is then demultiplexed. The multiphase outputs from the phase-locked loop (PLL) and CDR for MUX/DMUX allow the voltage-controlled oscillator (VCO) to operate at the relative lower parallel data stream rate instead of the much higher bit serial stream rate. For example, eight-phase 1.25-GHz clocks can be used to recover a serial data at 10 Gb/s for SONET systems. It has advantages including larger VCO jitter tolerance and ease of circuit design in a low-cost digital CMOS process instead of a Si bipolar or GaAs MESFET process. This paper presents a general ring oscillator topology for multiphase output and high-speed oscillation. A m CMOS PLL clock generator that incorporated the proposed VCO topology is designed to operate at 1.25 GHz with eight-phase outputs. The functional block diagram is shown in Fig. 2. The PLL includes a phase and frequency detector (PFD), charge pump, loop filter, VCO, and prescaler/divider. The output Manuscript received June 7, 2000; revised January 9, This work was supported by NSERC and CITO in Canada. L. Sun is with Lucent Technologies, Bell Labs, Allentown, PA USA. T. Kwasniewski is with the Department of Electronics, Carleton University, Ottawa, ON K1S 5B6, Canada. Publisher Item Identifier S (01) Fig. 2. Functional block diagram of the PLL clock generator. clock frequency ( MHz) can be synthesized from a or MHz reference clock with a corresponding feedback divider ratio of 8 or 32. Design considerations include low-voltage operation, low power consumption, monolithic integration, low timing jitter, and good process/temperature variation tolerance. In the next section of this paper, a general ring oscillator topology for high-speed operation and multiphase outputs is presented and analyzed. Section III describes a four-stage (eight-phase) subfeedback-loop-based differential ring oscillator. The PLL design and measurement results are presented in Section IV. Concluding remarks follow in Section V. II. MULTIPHASE OUTPUT RING OSCILLATORS The VCO is a critical building block in PLLs. High-frequency and RF voltage/current controlled oscillators can be implemented monolithically as LC oscillators, relaxation oscillators or ring oscillators. Although ring oscillators have poor phase noise characteristics compared to high- LC oscillators, they have the advantage of wider oscillation frequency range and a smaller die size. Ring oscillators are particularly attractive for multiphase clock signal generation required by many clock recovery circuits and high-speed sampling systems [1], [2]. For an -stage ring oscillator, the oscillation period of the ring is, where is the delay of each inverter stage. The minimum delay of each stage depends on the circuit structure, process parameters, and the size of transistors. The size of transistors affects the delay through its effect on driving strength, /01$ IEEE

2 SUN AND KWASNIEWSKI: MONOLITHIC CMOS PLL BASED ON A MULTIPHASE RING OSCILLATOR 911 Fig. 3. General topology of ring oscillator with subfeedback loops. Fig. 5. Block diagram of a five-stage ring oscillator with subfeedback loops (i = x = 3 case). Fig. 4. Redraw of Fig. 3 demonstrating the feedforward paths. self-loading, and loading to the previous stage. The improvement in speed can be obtained by a circuit optimization. However, the achievable improvement in speed is limited, especially for an oscillator with a long chain of inverters. To solve the conflict between speed (or tap-to-tap delay) and multiphase output, several techniques have been proposed [3] [6]. A VCO based on two-taps delay interpolating was proposed to provide largerange tuning without providing uniform tap-to-tap delay [3]. In [4], a two-dimensional coupled ring oscillator was developed to produce precise delays with subgate-delay resolution. Recently, a multiple-feedback-loop ring architecture was used for a threestage and four-stage ring oscillator design [5]. A single-ended multiphase ring oscillator was proposed using a negative skew delay scheme, suggesting an optimum skew delay of two inverter delays [6]. However, as will be shown later, the two-inverter skew delay is not always the optimum for long-chain ring oscillators. A. A General Topology of Multiphase Ring Oscillators Fig. 3 shows a general topology of multiphase ring oscillators with subfeedback loops [7]. The nodes and their interconnections have been correspondingly labeled. The fundamental idea is to use the interpolating inverters to construct intercoupled subfeedback loops. Each subfeedback loop contains an optimum number of inverters that keeps the circuit reliably oscillating at a higher speed. The phase relationship between inverter stages remains unchanged due to the symmetrical structure. Thus, reduced tap-to-tap delay can be achieved. We define as the feedback index. It is an integer representing the number of inverter stages in each subfeedback loop (e.g., when, there are three inverters in a subfeedback loop). The interpolating inverter can be incorporated into the major loop inverter circuitry with a separate input. The topology in Fig. 3 can be redrawn in Fig. 4 where the interpolating inverters are used to construct the fast paths (short cuts). We define as the feed-forward index in contrast to the feedback index. It is an integer representing the number Fig. 6. Combined single-stage equivalent circuit. of major loop inverters that the interpolating inverters pass over. The topologies of Figs. 3 and 4 are equivalent. The relation between and is. The block diagram of a five-stage single-ended ring oscillator is shown in Fig. 5 as an example of the topology for the (or ) case. The circuit contains a single slow loop and five subfeedback fast loops. Each subfeedback loop contains three inverter stages. Equivalently, the circuit can also be understood as a scheme where the delay of stages is the weighted sum of the delay through the slow path and the fast path. For example, the delay from node to node is the weighted sum of the slow path delay and the fast path delay. B. Model of Oscillation For an -stage ring oscillator in a stable oscillation mode, there exists a fixed phase relation between stages. Each stage contributes a phase delay of for a total, where is an odd integer with value smaller than. It represents a possible mode of oscillation. Another phase inversion required for the total phase shift of multiple of around the loop is provided by phase inversion in each inverter stage. For the differential ring oscillators with even number of stages, the phase inversion required for the total phase shift of a multiple of around the loop can be achieved by simply interchanging the differential outputs of the last inverter before feeding them back to the inputs. To find the optimum feedback index for a long-chain ring and the relative frequency variation, we model the signal path in the VCO with a first-order approximation, assuming its oscillation amplitude remains small and the waveform is sinusoidal-like. Fig. 6 shows a combined single-stage equivalent circuit diagram. and represent the equivalent output resistance and the total parasitic loading capacitance at node,

3 912 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 6, JUNE 2001 respectively. and represent the equivalent transconductance of the inverters in the main loop and subfeedback loop, respectively. We define as the phase difference between two adjacent nodes (e.g.,, for and ) and as the phase difference between node and node. Assuming all stages are the same, we have. Thus, the transfer function of a single stage can be found as (1) According to the Barkhausen criterion of oscillation [8], the ring oscillator would oscillate if the loop has unity voltage gain and phase shift of or a multiple of. Although there may exist some possible modes for long-chain ring, only those modes with enough loop gain can sustain oscillation. Since we want single-mode operation, loop gain should be designed to be smaller than one for all the undesired modes. From (1), the minimum required gain of each stage can be written as and the approximate oscillation frequency can be expressed as where The first term of (3) is the oscillation frequency of a conventional ring oscillator. The second term corresponds to the frequency increment or decrement. Considering that an oscillator is a large signal nonlinear system, as the amplitude grows, transconductance degrades; furthermore, output resistance and capacitance deviate from their value near the quiescent biasing point. Equation (3) actually overestimates the real oscillation frequency. However, we are more interested in comparing the relative frequency improvement between different topologies rather than calculating the absolute oscillation frequency. Equation (3) can be used to qualitatively estimate the relative frequency increase/decrease ( ) compared to the conventional ring topology. We have where and are the total loading capacitance of each stage for the subfeedback based topology and the conventional single loop topology, respectively. represents the average strength of the interpolating inverters. is the operating frequency for the conventional single loop topology. We have assumed that remains the same. (2) (3) (4) (5) Fig. 7. Seven-stage ring oscillator transient waveforms for different feedback index i. C. Increasing the Oscillation Frequency To achieve a large relative frequency increment, the interpolating inverters should be introduced without a significant increase of the loading capacitance. Furthermore, in (4) should be positive. Since is fixed for an -stage ring oscillator during stable oscillation, whether oscillation frequency is increased or decreased depends on the feedback index, which is the number of inverters in a subfeedback loop. The subfeedback loop can contain an even ( ) or odd ( ) number of inverters. An odd number of inverters inside a subfeedback loop has a positive value, thus increases the operating frequency, while an even number ( ) causes a decrease in the operating frequency. For a long-chain ring, there exists an optimum feedback index which gives the highest operating frequency. This can be easily confirmed with HSPICE large-signal transient simulations. A simple single-ended inverter was used as a delay stage in the large-signal simulations. The device sizes of inverters in the major loop are 30 m/0.6 m( ) and 10 m/0.6 m for pmos and nmos, respectively, while the device sizes of the interpolating inverters are 15 m/0.6 m (pmos) and 5 m/0.6 m (nmos), respectively. The simulations were run with 0.5 m digital CMOS process parameters and a power supply of 3.3 V for. Fig. 7 shows the oscillation waveforms for corresponding to different values. When the subfeedback loop contains three ( ) or five ( ) inverters,, and the frequency is increased compared to a conventional seven-stage single-loop ring oscillator. However, when the subfeedback loop contains four ( ) or six ( ) inverters, frequency is decreased

4 SUN AND KWASNIEWSKI: MONOLITHIC CMOS PLL BASED ON A MULTIPHASE RING OSCILLATOR 913 TABLE I OSCILLATION FREQUENCY CORRESPONDING TO PARAMETERS i, x, AND k FOR N = 7 AND 9 Fig. 9. Interpolating inverter S pass over three major loop inverters (x =3 case). Fig. 10. Combined single stage with multiple feedback. Fig. 8. Oscillation frequency versus stage number N with feedback index i as parameter. due to the fact that is negative. Since for has a larger value compared to that for, a higher oscillation frequency is achieved. Table I lists the corresponding values of the simulated oscillation frequency and parameters,, and for and. As explained earlier, is the feedforward index. The positive values of and corresponding frequency are highlighted. Fig. 8 summarizes the simulation results illustrating oscillation frequency versus with as a parameter. For, the highest oscillation frequency is achieved at. However, for, the highest oscillation frequency is achieved at.for, we get the highest frequency at. The results confirm the prediction from the calculation of magnitude. From Fig. 7 we found that although the circuit achieves highest speed when, it produces a sinusoidal-like waveform when ( ). Similar phenomenon can be observed for other values, but all corresponding to case, as shown in Fig. 9. Since its total power consumption is actually lower than the case corresponding to the highest frequency, a higher equivalent quality factor is expected for the case. For, improved speed is achieved when or. If two feedback indices are combined in one circuit as shown in Fig. 10, an even higher oscillation frequency can be obtained. This can be extended to a longer chain ring to form multifeedback loops, for example, combining in the nine stages ( ) ring. It should be noted that the improved speed for a constant output voltage swing comes at the expense of greater power consumption due to the time overlap when both nmos and pmos are on. We are more interested in power efficiency rather than power consumption in comparison of oscillators running at different speed. The power efficiency can be measured by the product of the oscillation period and power consumption. Taking as example, the period power product for are 13.2, 27.7, and 26.1 pj, respectively. The conventional ( ) single-ring structure has highest power efficiency overall. Among the subfeedback-loop-based structure, (, ) case has the highest efficiency. D. Frequency Tuning In additional to the feature of improved speed, we observe from (3) that the oscillation frequency of an -stage ring oscillator with a fixed feedback index can be tuned by varying any one of three parameters: loading capacitance, loading resistance, and relative strength of interpolating inverters. Capacitive tuning has the drawback of lowering the maximum speed of operation because the minimum value of capacitor still loads the circuit. Although a resistive tuning can provide a large frequency variation, it causes a voltage swing and voltage gain variation [9]. When transistors operating in the triode region are used as loading resistors, their nonlinearity degrades the common-mode noise rejection for a differential circuit. According to (3), the oscillation frequency of the subfeedback-loop-based ring oscillators linearly depends on. When is controlled by an external voltage, the tuning range is. This tuning scheme is especially useful when loading resistors in the delay stages are implemented with linear resistors (e.g., poly resistors) to improve the common-mode noise rejection.

5 914 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 6, JUNE 2001 Fig. 11. Eight-phase-output ring oscillator based on three-stage (i = 3) subfeedback loops. Fig. 14. ICO differential stage, V I, and bias circuit. Fig. 12. Three-dimensional representation of the ring oscillator from Fig. 11. Fig. 15. PFD, charge pump, and loop filter. Fig. 13. Phase relationship of the circuit in Fig. 11. III. DESIGN OF AN EIGHT-PHASE-OUTPUT RING OSCILLATOR The topology in Fig. 3 was used to design a four-stage differential ring oscillator as shown in Fig. 11. Compared with conventional ring oscillators, four inverters are interpolated to construct the subfeedback loops. With feedback index, each subfeedback loop contains three inverters (M1 M2 S4; M3 M4 S2; M2 M3 S1; M4 M1 S3) and is established as a fast loop. The main feedback loop with four stages is the slow loop. By redrawing the circuit in three dimensions as shown in Fig. 12, the subfeedback loops can be more easily viewed (single-ended inverters are plotted for simplicity). It should be noted that stages in altitude and latitude are designed not to oscillate in a two-stage ring oscillator mode to ensure reliable oscillation and reduction of phase noise. Fig. 13 shows the phase relationship of eight output signals (when matched delay stages and loading are used). Imposing these phase relations to (3), the minimum required dc gain is, which can be used to calculate the initial value of transistors for design and simulation. Since minimum dc gain is not related to, it is much easier to maintain oscillation when is controlled with an external control signal. A combined single delay stage of the ICO core circuit is shown in Fig. 14. It consists of a major loop inverter and an interpolating inverter. Fully differential inverters are used to reduce the sensitivity to power supply fluctuation and substrate noise and to reduce the distortion of the duty cycle. The two nmos source-coupled differential pairs share the same loads, but have separated tail current sources. Frequency tuning can be accomplished with controlled by a single-ended signal or both controlled (push pull) by a differential signal. In this design, is connected to a proportional-to-absolute temperature (PTAT) current reference and is controlled by the charge pump/loop filter output signal through a voltage-to-current ( ) converter for frequency and phase locking. The oscillator is optimized to operate at the required output frequency when. The circuit is also shown in Fig. 14. The PTAT reference circuit reduces the VCO s sensitivity to temperature and process variation. In the PTAT bias reference, placing resistor to the pmos source and tying the source and n-well of each pmos transistors eliminate body effect. By connecting a diode-connected pmos transistor in shunt with an equal size biased pmos transistor, the linearity of loading can be improved [10]. 200 ppm/ C of temperature sensitivity and 6%/V of power supply sensitivity without the use of a regulator is achieved with a good frequency control linearity. IV. PLL DESIGN AND MEASUREMENT RESULTS The PFD is based on a conventional three-state phase detector (PD) shown in Fig. 15. The circuit consists of two edge-triggered resettable D-flip-flops which were implemented using dynamic logic circuitry. In order to minimize the dead zone associated with the three-state PFD, extra delay is introduced in the reset path through inverters. The charge pump and loop filter are also shown in Fig. 15. The UP and DN signals from the PFD switch the corresponding current sources onto node, thus delivering a charge to adjust up or down. Both current sources are mirrored from a bandgap current. When neither nor is connected to, they are biased by the unity-gain amplifier [11]. It suppresses

6 SUN AND KWASNIEWSKI: MONOLITHIC CMOS PLL BASED ON A MULTIPHASE RING OSCILLATOR 915 Fig. 16. Die photograph of the PLL clock generator. Fig. 18. PLL jitter histogram. TABLE II SUMMARY OF MEASURED PLL CLOCK GENERATOR PERFORMANCE Fig. 17. Measurement result of the ICO (in PLL) transfer characteristic. the charge sharing from the parasitic capacitance on node or, thus reducing the spike on the loop filter. The prescaler used to divide the VCO output by factor 2 is designed using a true-single-phase clock (TSPC) D-flip-flops [12]. The transistors size is optimized to achieve high-speed operation. The frequency operating range of the prescaler is from 400 MHz to 3 GHz with a power consumption of 6 mw at maximum frequency. The divide by 8/32 divider is also based on the dynamic flip-flops which are connected as a ripple counter and resynchronized at the output. The bandwidth of the PLL affects the stability, the lock-in time, and the suppression of phase noise from the VCO. The loop bandwidth is chosen to be 2 MHz with resistor of 40 k and charge pump current of 20 A. and are 240 and 1 pf, respectively. The PLL clock generator was implemented monolithically in a m single-poly three-metal CMOS technology [13]. Fig. 16 shows the die photo of PLL clock generator. By varying the input reference frequency, the ICO transfer characteristic were measured and shown in Fig. 17. The ICO has a good control linearity. The jitter histogram of the PLL was measured with other transceiver blocks active on chip. The tracking jitter at 1.25-GHz output is 11 ps (RMS) and 80 ps (peak-to-peak) with power consumption of 109 mw for a 3.3-V supply (Fig. 18). Table II summarizes the measurement results. V. CONCLUSION A general ring oscillator topology for multiphase output has been presented and analyzed. The topology uses the interpolating inverter stages to construct fast loops for long-chain ring oscillators to achieve both higher speed and multiphase outputs. The analysis leads to a relationship between relative oscillation frequency increment/decrement and the feedback index, which is the number of inverters inside a subfeedback loop. An odd number of inverter stages inside a subfeedback loop can increase the operating frequency. For a long-chain ring, there exist optimum values which give the highest operating frequency and highest power efficiency, respectively. A 1.25-GHz monolithic CMOS PLL clock generator prototype was designed for a data transceiver. The monolithic PLL consists of a ring oscillator, divider, PFD, charge pump, and on-chip loop filter. The design accommodates process, supply voltage, and temperature variations. The voltage controlled oscillator incorporates a four-stage differential ring structure with subfeedback loops embedded to speed up and tune the circuit. It has a linear control characteristics, eight-phase outputs, and wide tuning range. The fully integrated PLL was fabricated in a m CMOS process, occupies an active area of 1 mm, and consumes about 100 mw operating from a 3.3-V supply. A RMS tracking jitter of 11 ps was measured.

7 916 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 6, JUNE 2001 ACKNOWLEDGMENT The authors would like to thank V. Lee, D. Cartina, K. Iniewski, B. Gerson, M. Chua, R. Zavari, and Y. Xu of PMC-Sierra, Inc., Burnaby, Canada, for their support. [12] J. Yuan and C. Svensson, High-speed CMOS circuit technique, IEEE J. Solid-State Circuits, vol. 24, pp , Feb [13] L. Sun and T. Kwasniewski, A 1.25-GHz 0.35-m monolithic CMOS PLL clock generator for data communications, in Proc. IEEE Custom Integrated Circuits Conf., 1999, pp REFERENCES [1] K. B. Kim, D. Helman, and P. Gray, A 30-MHz hybrid analog digital clock recovery circuit in 2-m CMOS, IEEE J. Solid-State Circuits, vol. 25, pp , Dec [2] S. K. Enam and A. Abidi, NMOS ICs for clock and data regeneration in gigabit-per-second optical-fiber receivers, IEEE J. Solid-State Circuits, vol. 27, pp , Dec [3] S. K. Enam and A. Abidi, A gigahertz voltage-controlled ring oscillator, Electron. Lett., vol. 22, pp , June [4] J. G. Maneatis and M. A. Horowitz, Precise delay generation using coupled oscillators, IEEE J. Solid-State Circuits, vol. 28, pp , Dec [5] S. J. Lee, B. Kim, and K. Lee, A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme, IEEE J. Solid-State Circuits, vol. 32, pp , Feb [6] D. Jeong, S. Chai, W. Sing, and G. Cho, CMOS current controlled oscillators using multiple feedback loop ring architectures, in ISSCC Dig. Tech. Papers, 1997, pp [7] L. Sun, T. Kwasniewski, and K. Iniewski, A quadrature output voltagecontrolled ring oscillator based on three-stage subfeedback loops, in Proc. IEEE Int. Symp. Circuits and Syst. (ISCAS), vol. 2, 1999, pp [8] A. B. Grebene, Bipolar and MOS Analog Integrated Circuit Design. New York: Wiley Interscience, 1984, ch. 11. [9] B. Razavi, Design of monolithic phase-locked loops and clock recovery circuits A tutorial, in Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design. Piscataway, NJ: IEEE Press, [10] J. G. Maneatis, Low-jitter process-independent DLL and PLL based on self-biased techniques, IEEE J. Solid-State Circuits, vol. 31, pp , Nov [11] M. G. Johnson and E. L. Hudson, A variable delay line PLL for CPU coprocessor synchronization, IEEE J. Solid-State Circuits, vol. 23, pp , Oct Lizhong Sun received the M.Eng. and Ph.D. degrees in electrical engineering from McGill University, Montreal, PQ, Canada, and Carleton University, Ottawa, ON, Canada, in 1994 and 1999, respectively. From 1994 to 1996, he was with OZ Optics, Carp, ON, Canada, working on fiber optics and optoelectronic components. In the summer of 1998, he was with PMC-Sierra, Burnaby, BC, Canada, working on CMOS phase-locked loops for frequency synthesis and data recovery. In 1999, he joined Bell Labs, Lucent Technologies, Allentown, PA, as a Member of Technical Staff. He is currently working on high-speed analog and mixed-signal IC design. Tadeusz A. Kwasniewski (M 86) received the Ph.D. and M.S. degrees from the Institute of Nuclear Research and Warsaw University of Technology, Poland, in 1974 and 1980, respectively. He worked as a Research and Development Engineer in Warsaw s Institute of Nuclear Research and VOEST Alpine in Austria. In 1983, he joined Lakehead University and in 1985, Carleton University, Ottawa, ON, Canada. His research interests include CMOS radio circuits and signal processing architectures. He is currently with PMC-Sierra, Burnaby, BC, Canada, on leave of absence from Carleton University. He is currently working on high-speed CMOS data recovery and synthesis circuits.