2kW Telecom SMPS Design Guidelines. IFAT PMM Application & Systems Francesco Di Domenico Vladimir Scarpa Juan Sanchez

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1 2kW Telecom SMPS Design Guidelines IFAT PMM Application & Systems Francesco Di Domenico Vladimir Scarpa Juan Sanchez

2 Table of contents Telecom Systems and Switch Mode Power Supplies 48V 2kW Telecom Rectifier technical specification Design procedure Design of HV DC/DC Converter: ZVS Phase Shift Full Bridge Conclusions 9/27/2012 Page 2

3 Typical DC power supply system for Telecom equipment 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 3

4 Typical hybrid solar DC power supply system for Telecom equipment 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 4

5 Focus of the workshop: AC/DC Telecom Rectifier 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 5

6 Key Features High and Flat Efficiency Curve 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 6

7 Key Feautures Highest efficiency in minimum space Digital Control & Communication 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 7

8 Key Feautures Modular approach (power shelf) High MTBF requirements: > hours at Tamb=25 C (according to SR-332 calculation methodology) 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 8

9 Key features Accurate control of the charge curve SCR BC SMR BC CONTROL & MONITORING UNITS 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 9

10 Table of contents Telecom Systems and Switch Mode Power Supplies 48V 2kW Telecom Rectifier technical specification Design procedure Design of HV DC/DC Converter: ZVS Phase Shift Full Bridge Conclusions 9/27/2012 Page 10

11 Typical Technical Specification Requirements for a 48V /2kW Telecom Rectifier: AC input 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 11

12 Typical Technical Specification Requirements for a 48V /2kW Telecom Rectifier: DC output 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 12

13 Other typical requirements 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 13

14 Safety & EMC Standards 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 14

15 Table of contents Telecom Systems and Switch Mode Power Supplies 48V 2kW Telecom Rectifier main requirements Design Procedure Design of HV DC/DC Converter: ZVS Phase Shift Full Bridge Conclusions 9/27/2012 Page 15

16 Principle Block Schematic of a Switch Mode Telecom Rectifier Isolated HV DC/DC Stage AC V HBr- Driver SR-IC Driver SR-IC Driver 53.5V PFC Controller PWM Controller PFC stage PWM or resonant stage Secondary rectification P P Av I V 9/27/2012 Page 16

17 Inside a Telecom Rectifier 9/27/2012

18 Designing a 2kW CCM PFC for Telecom Applications AC V HBr- Driver SR-IC Driver SR-IC Driver 53.5V PFC Controller PWM Controller

19 PFC Design in 6 Steps Rectifying Bridge 2 Filter Inductor 3 Output Capacitor 4 Boost Switch 5 SiC Diode 6 Bypass Diode 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 19

20 Input Parameters Parameter Input voltage Value Vac Pmax High Line ( V) Max Input Current Bulk voltage Switching frequency 2 kw 10.7 Arms Vdc 65 khz Output Voltage Ripple 5% Current Ripple 20% Max. Ambient Temp. 70 C Max. Junction Temp. 125 C 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 20

21 Table of contents Circuit Design Calculated Efficiency Curve Experimental Results 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 21

22 1 - Bridge Rectifier Average current=avg. input current: I BR = Iin. avg = Iin.. rms 2 2 π 10.7A Power dissipation: P BR = 2 V f. BR I BR 21.4W 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 22

23 2 - Filter Inductor: Peak input current: I PK = 2I in.. rms 16A Peak Current Max. Current Current ripple: I = 20% HF I PK 3.2A Peak Current + ripple: I HF I L. MAX = I PK A Ripple 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 23

24 Filter Inductor: At peak current, ripple=20%: I HF = 20% 2I in.. rms 3.2A δ Tsw Duty cycle, for Uin.min: U min =1 in U out Minimum Inductance: L 1 VL t = I V = in T I HF SW 450µH 20%Ipeak 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 24

25 3 - Output Capacitor Hold up time: No V in for 20ms P o =P o.max U out >U out.min U out.min =300V Minimum capacitance value: C out Pout.max Tac I t U out.min 6.7A 20ms = = = C out > 1.3mF U U U 100V out out.min 2*fac voltage ripple in output: U Pout U in 2π f.max.min out = = 15 ac C out V U out =4% 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 25

26 4 - Boost Switch For R ds.on Optimization: I in I cond. sw avg Pin = δ 230V = U in avg = 230V 4.7A I con.sw Conduction losses estimation: P 2 cond. sw = Rds. on _125 C Icond. sw Voltage class: = 535V U sw xu out 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 26

27 4.1 - CoolMOS P6 vs. CoolMOS C6 Lower Qg less driver losses Higher threshold voltage less turn-off losses Smaller internal Rg faster commutation 190 mω parts, Rg=5Ω CoolMOS C6 CoolMOS P6 CoolMOS C6 CoolMOS P6 E=20µJ Ex65kHz=1.3W 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 27

28 4.2 Rds_on Optimization Due to power level 2 switches in parallel! Tj=125 C Optimum Rds_on~200mΩ For each switch Switching losses 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 28

29 4.3 - Thermal Design Switch Vin=230Vac: P losses = 4.4 W per part Switch Vin=185Vac: P losses = 7.2 W per part Rth,JC of each part: R TH,JC = 2.6 C/W T j <125 C R TH,JC R TH,CA Case R TH,CA < 5 C/W T amb =70 C 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 29

30 5 - Boost Diode Si Diode Price Surge current capability SiC Shottky Diode No switching losses Less losses in the switch 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 30

31 5.1 - ThinQ Gen 5 SiC Diodes 650V SiC Diode Thin-wafer technology Wire bond Q C G2 Sw. Losses G3 bond metal Schottky contact Drift layer SiC Substrate R bulk G5 Cond. Losses V f Backside metal Simplified schematic, with no merged pn junction. V F = V th + R diff I F η % Comparative Efficiency Gen 5 Gen 3 Gen 2 Load [W] 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 31

32 5.3 Choice of the Current Class Average current I P = U out di. avg = 5 out A RMS Current I di. rms = 2 Iin. rms (1 D) = 7. 5A Dissipated power 2 P di = Vth I di. avg + Rdiff I di. rms 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 32 Junction Temp. [C]

33 6 - Bypass diode Output capacitor is fully charged during 1 semi-cycle=10ms: I surge = U T out ac C / 2 out = 400V 1.3mF 10 ms 53A 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 33

34 Table of contents Losses Calculation Calculated Efficiency Curve Experimental Results 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 34

35 Losses and Circuit Pbr=15.4W Pind=10.1W Psw=8.7W η 10% = P.max=850W η 20% = 98.2% η 50% = 98.1% η 100% = 97.9% 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 35

36 Table of contents 2kW PFC Circuit Design Losses Calculation Experimental Results 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 36

37 Efficiency Measurement 1kW, 1x190mΩ CoolMOS, 1x6A Gen 5 same semiconductor effort CoolMOS P6 CoolMOS C6 CoolMOS P6 CoolMOS C6 T HS 60 C f sw 65kHz Rg,ext 10Ω 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 37

38 Efficiency Measurement Low Line (up to 350W) CoolMOS P6 CoolMOS C6 CoolMOS P6 CoolMOS C6 T HS 60 C f sw 65kHz Rg,ext 10Ω 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 38

39 Table of contents Telecom Systems and Switch Mode Power Supplies 48V 2kW Telecom Rectifier main requirements Design procedure Design of HV DC/DC Converter: ZVS Phase Shift Full Bridge Conclusions 9/27/2012 Page 39

40 Principle Block Schematic of a Switch Mode Telecom Rectifier AC V HBr- Driver SR-IC Driver SR-IC Driver 53.5V PFC Controller PWM Controller 9/27/2012 Page 40

41 HV DC/DC Stage: choice of the topology Figure of merit ZVS PF FB vs. HB LLC Phase Shift FB LLC HB /27/2012

42 ZVS Phase Shift Full Bridge 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 42

43 ZV PS FB - principle of operation power transfer phase over A/D discharge C oss of C and charge C oss of D I PRIM commutation to body diode of C free-wheeling phase charge C oss of A and discharge C oss of B commutation to body diode of B power transfer phase over C/B 0A primary current changes direction 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 43

44 ZVS PS FB: main components dimensioning and inherent topics Main Transformer FB HV MOSFETs Resonant Choke Output Choke Output Capacitance Synchronous Rectification Topology Power MOSFETs 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 44

45 2kW ZVS PS FB Reference Design board description DC/DC converter with 300V-420V input 45V-56V output voltage Fsw=100kHz up to 2000W output power 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 45

46 Schematic Output filter Main trafo Synchronous rectification Full Bridge Lr=res. inductance 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 46

47 HV DC/DC Converter: Main Design Specifications Description Minimum Typical Maximum Input Voltage 300Vdc 400Vdc 410Vdc Output Voltage 45Vdc 54Vdc 56Vdc Output Power Full Load Efficiency 95% Switching Frequency seen by L out choke 200kHz 2000W δ cycle 70% Dynamic Output Voltage regulation (0-90% Load step) Vtrans= ±5%V out_max =2.8V Vout ripple 100mV pk-pk 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 47

48 Main Transformer Design: Center Tap vs. Current Doubler 30 Center Tap 25 Current Doubler_1 20 Current Doubler_ Pcu_sec Ptr_tot Pcu_Lout Pcore_Lout Ptotal_Lout Ptotal_magnetics 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 48

49 Main Transformer Design: core selection Area Product Formula Applying this rule of thumb formula Ae 200mm 2 PQ/40/40 core A e =201mm² V e =20500mm³ 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 49

50 Main Transformer Design: turn ratio, Np, Ns Turn Ratio α1=np/ns 5 Primary turns Np 20 Secondary Turns Ns=Np/α1 4 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 50

51 Kaschke main transformer core type: PQ40/40 core material: 3C96 nominal inductance: 1mH ±15% ratio of turns: 20 : 4 : 4 dielectric strength (50Hz/1s): 3kV operating temperature: -25 C till +125 C storage temperature: -25 C till +85 C Kaschke Components GmbH Rudolf-Winkel-Str Göttingen Germany dimensions in [mm] 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 51

52 Choice of the power devices: 650V 80mOhm CFD2 9/27/2012 Page 52

53 Losses spread on HV MOSFETs in a Soft Switching topology (fsw=100khz & 200Khz) Primary mosfets 100Khz (P=0.589W) Primary mosfets 100Khz (P=10.52W) 68.4% (0..4W) 16% (0.09W) 13.1% (0.07W) Conduction Losses Turn on losses Turn off losses Driving losses 3.8% 13.7% (0.4W) (1.44W) 80% (8.4W) Conduction Losses Turn on losses Turn off losses Driving losses Primary mosfets Pmax 200Khz (P=1.05W) 76.7% (0.8W) 8.2% 5.4% (0,056W) (0,09W 9.7% (0,1W) Q g Conduction Losses Turn on losses Turn off losses Driving losses 4.4% (0.88W) 22.8% (2.88W) Primary mosfets 200Khz (P=12.64W) 6.4% (0.8W) 66.4% (8.4W) R ds,on Conduction Losses Turn on losses Turn off losses Driving losses 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 53

54 The transition time: the ZVS window Vgs high side Q g Vds low side Q oss 90% V DS 10% V DS t 1 t 2 t 3 td_off = t 1 -> t 2 td_vdstrans = t 2 -> t 3 td_total = t 1 -> t 3 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 54

55 MOSFET key parameters in ZVS design: Body diode Vf involved in conduction losses at turn-on Qrr/trr involved in reliability issues on the leg with less resonant energy available. Reverse recovery current 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 55

56 Typical hard commutation on body diode still not fully recovered Short-through like, but it is a current flows through HS MOSFET and reverse recovery current for body diode of LS MOSFET V GS,1 V GS,2 Q 1 I DS,1 C r L r I DS2 I d,2 XR ds,on =0 Body diode can t turn off completely Reverse recovery current L m V DS,2 Q 2 V DS,1 Over-shoot of VDS Extremely high dv/dt and di/dt 9/27/2012 Page 56

57 Completely Reverse Recovery MOSFET No voltage, no current ringing Above specified current level, the body diode is completely reverse recovered 9/27/2012 Page 57

58 Un-Completely Reverse Recovery MOSFET Voltage/current ringing Under specified current level, the body diode is un-completely reverse recovery 9/27/2012 Page 58

59 Choice of the FB power MOSFET: why CFD2? Qg benefits about 30% reduction of Q g over whole R DS(on) range BENEFITS: lower driving losses faster switching 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 59

60 Choice of the FB power MOSFET: why CFD2? Qrr benefits CFD2 shows less Q rr in comparison to CFD and comparable competitor products BENEFITS: less stress on MOSFET during commutation makes device suitable for soft switching application 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 60

61 The resonant tank Total resonant capacitance Energy stored in the resonant capacitance Energy which must be provided by the resonant inductance: In the case of CFD2, with the goal to achieve ZVS down to 20%Pmax: Lr=30µH 9/27/2012 Page 61

62 Kool-mu resonant choke 9/27/2012 Page 62

63 Output Choke Minimum needed L out where 9/27/2012 Page 63

64 MPP Output choke 9/27/2012 Page 64

65 Output Capacitance Total Cout selected according to load transient requirement Time needed by Lout to change 90% of its full load current: Selected capacitors 470µF KZE miniaturized (ESR=0.028Ω, I ripple =2.3A) Final choice: N=6 470µF, 63V, KZE capacitors 9/27/2012 Page 65

66 Synchronous Rectification AC V HBr- Driver SR-IC Driver SR-IC Driver 53.5V PFC Controller PWM Controller 9/27/2012 Page 66

67 Synchronous Rectification Possible Applications 12V systems: Computing (PC Silver box, Server SMPS, Gaming) - 40V, 60V, 75V, 80V MOSFETs 12V-24V systems: - 100V, 120V MOSFETs Notebook adapter, industrial SMPS 24V-48V systems: Telecom, industrial SMPS - 150V, 200V, 250V MOSFETs 60V-100V systems: - 150V, 200V, 250V MOSFETs LCD 11/03/2010

68 SMPS - What is be the trend for the future? Server Power supply example Up to now EFFICIENCY Future trend EFFICIENCY & POWER DENSITY 5 years ago Now 5 years in the future 10W / inch³ 30W / inch³ Set date Page 68

69 How to achieve? Technology improvement Reduction of FOM=R DS(on) x Q g Higher efficiency Lower power losses Smaller heatsinks Package Shrink TO220 SuperSO8 Blade Set date Page 69

70 Principle of Synchronous Rectification Set date Page 70 Copyright Infineon Technologies All rights reserved.

71 What is synchronous rectification??? Replacement of the diodes by MOSFETs on the secondary side of a SMPS a MOSFET (sync. FET) replaces a diode in its electrical functionality the sync. FET has NO control function no active switching of current (gate) switching speed has no influence on efficiency! no additional function compared to the diode is realized with a gate-source short on the sync. FET, the system stays electrically functional June 2010

72 Optimized device selection for Synchronous Rectification Set date Page 72 Copyright Infineon Technologies All rights reserved.

73 Analyzing the SR turn-off behavior U DSpeak V T Gate turn-on reverse recovery behavior V DS dv IC ( t = ) dt C oss I init I DS V DS V G Free oszillation V GS V D V ind Q rr * V GS MOSFET body diode ontime Q oss I DS time V ind I rev_peak t D tramp t Qrr*+Qoss di dt = V DS ( t) V L T

74 Calculation of power losses in SR (I) Conducting losses P v _ cond = I 2 RMS R DS ( on) Gate losses P v _ gate = Q g U g f sw Body diode conduction loss P V _ BD _ cond = U D I D tbd _ on f sw

75 Development of a power-loss model Assumptions for following model Fast primary side switches Current commutation on sec. side is inductively limited Upeak Icomm UDS E C = 1 C V 2 2 Utrafo di/dt=const Q oss Q * rr ID time Irev_ peak t Ipeak t Ipeak 2 t Upeak E L = 1 L I 2 t rev

76 Synchronous Rectification Losses Summary Conducting losses P v _ cond = Body diode conduction loss P I 2 RMS R DS ( on) V _ BD _ cond = V D I D t BD _ on f sw Conduction Gate losses P v _ gate = Q Turn-off reverse recovery losses P sw T g V g f sw ( 1 2 Q ) oss + Q rr fsw = V * Switching

77 Power Loss Distribution power losses per MOSFET [W] Distribution of power losses in SR BSC031N06NS3 G, switching frequency = 125kHz, transformer voltage = 30V, Vout=12V output capacitance losses gate drive losses conduction losses output currrent [A] Switching losses dominate at low loads Conduction losses dominate at high loads Set date

78 The key for further performance improvement Power Loss [W] Power Losses vs Rds(on) V_Transformer=135V; Vgate=10V; Fsw=100KHz; Iout=45A switching losses dominated Pswitching Pconduction P_Total balanced operation Optimum R ds(on) ~ 4.5 mω 2xIPP110N20N3 G (R ds(on)max = 11 mω) conduction losses dominated Total SR Rds(on) [mohm] R DS ( on) _ opt FOM = Qg f sw V + 1 FOM 2 I Set date Page 78 g 2 RMS Qoss V T f sw

79 Design considerations Set date Page 79 Copyright Infineon Technologies All rights reserved.

80 Turn-off voltage overshoot V DS overshoot V DS V GS di/dt Set date Page 80

81 Qrr impact - measurement Qrr & Overshoot vs. Body Diode On Time IPP05CN10N 60 nc 50 nc Device not fully off Shoot through 120 V 100 V 40 nc 80 V Qrr 30 nc 60 V 20 nc Qrr 40 V Overshoot 10 nc Poly. (Qrr) 20 V Poly. (Overshoot) 0 nc 0 V 0 ns 20 ns 40 ns 60 ns 80 ns 100 ns 120 ns 140 ns 160 ns Body Diode On Time Overshoot Lower body diode on time -> lower Q rr -> lower overshoot -> lower losses -> better efficiency Qrr dependencies are complex: Qrr increases with t Body and di/dt Parallel schottky diode will reduce Qrr but increase leakage current Infineon new 40V introduce Schottky-like diode technologies

82 Impact of the package Set date Page 82 Copyright Infineon Technologies All rights reserved.

83 Highest Efficiency package contribution The lower the product resistance the higher the package contribution Set date

84 Highest Efficiency Reduction of FOM Immense reduction of FOM for SuperSO8 packaging Comparison - Figure of Merit (FOM) Current 60V OptiMOS technology -45% reduction 400 FOM [mohm x nc] TO220 SuperSO8 0 FOM(Qg) FOM(Qoss) Set date

85 Highest Efficiency SuperSO8 solutions allow: Measurement in Server DC/DC -Lower package resistance -Less parasitics efficiency [%] Higher efficiency through lower power losses BSC047N08NS3 IPP057N08N3 -Lower turnoff losses output current [A] Conditions: 12V - 600W server PSU, 100kHz switching frequency, half bridge, current doubler rect. Set date

86 Outstanding Switching Behavior High side switch L OUT Transformer C OUT GND Low side switch power-commutation loop SuperSO8 layouts minimize parasitic loop inductances turn-off losses are minimized ringing is minimized efficiency of snubber circuit is maximized Set date

87 Outstanding Switching Behavior 90 overshoot [V] UDS VDS voltage overshoot voltage overshoot 10V reduction output current [A] Conditions: Half Bridge DC/DC converter 12V, fsw=100khz, 100V MOSFETs Set date

88 Summary Synchronous Rectification brings out outstanding power savings. Newest Optimos MOSFETs technologies widens the range of applications and conditions where SR is advantegeous. The most important loss contributions are coming from the Rds(on) of the device and Eoss and Qrr. For a given technology, the right MOSFET Rds(on) working at a balanced operation (tradeoff between switching and conduction losses) will offer the best performance. Qrr is a parameter with complex dependencies that hardly can be characterized by one simple value in the specifications. Adoption of new Leadless packages like TO-220 makes possible to extract the benefits from the advances in silicon technology

89 Table of contents Telecom Systems and Switch Mode Power Supplies 48V 2kW Telecom Rectifier main requirements Design procedure Design of HV DC/DC Converter: ZVS Phase Shift Full Bridge Conclusions 9/27/2012 Page 89

90 PFC AC V HBr- Driver SR-IC Driver SR-IC Driver 53.5V PFC Controller PWM Controller 9/27/2012 Page 90

91 PFC efficiency η 10% = 97.9% η 20% = η 50% = 98.1% P.max=850W η 100% = 97.9% 9/27/2012 Page 91

92 ZVS Phase Shift Full Bridge with Synchronous Rectification AC V HBr- Driver SR-IC Driver SR-IC Driver 53.5V PFC Controller PWM Controller 9/27/2012 Page 92

93 ZVS Phase Shift Full Bridge IFX reference design main components full bridge MOSFETs: IFX CoolMOS TM IPW65R080CFD synchronous rectification MOSFETs: IFX OptiMOS TM IPP110N20N3 auxiliary converter: Infineon ICE3A0365 controller: Texas Instruments UCC28950 gate driver: Texas Instruments UCC27324 main transformer: Kaschke Components GmbH PQ40/40 ferrite core (center tap) resonant choke: Magnetics Inc. Kool-Mµ output choke: Magnetics Inc. Molypermalloy 9/27/2012 Copyright Infineon Technologies All rights reserved. Page 93

94 CFD2 80mOhm in 2kW ZVS PS FB board efficiency measurements Efficiency -CFD2 80mOhm in 54V/37A ZVS Phase Shift Full Bridge 98 CFD2 80mOhm 100Khz EFFICIENCY [%] OUTPUT POWER [W] 9/27/2012 Page 94

95 Target Efficiency achieved! 9/27/2012 Page 95

96

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