Components. Active Components. Passive Components

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1 Components Active Components diodes, transistors, integrated circuits optoelectronics analog, digital, power based on semiconductor materials Passive Components Resistors Capacitors Inductors

2 Active Components Increase in active device performance will place heavy demands throughout all aspects of packaging to meet the performance projections Semiconductor Industry Assoc. (SIA) roadmap projects speeds at 1 GHz and power at 200 W within 8 years, although performance has already outstripped the roadmap) New devices (SiC,GaAs, etc) and optoelectronic devices and integration will continue to challenge packaging designers

3 Active Part Classification By semiconductor material-si, GaAs, SiC, other III-V and II-VI compounds By construction technology-cmos, bipolar, BiMOS, FET By device integration-transistor, integrated circuit, level of integration (LSI, VLSI, ULSI), and type( memory, microprocessor) By application-digital, analogue, mixed signal, power, high speed, microwave

4 Critical Performance Attributes Speed Level of integration ( number of gates) Power ( from 1.2 to hundreds of volts) Device feature size ( 1.5 to submicron) Number of interconnects Number of I/Os

5 Representation of a MOSFET

6 CMOS Gate Construction VDD VDD

7 Processes in IC Fabrication E-beam deposition Sputtering Chemical Vapor Deposition MOCVD ( metallorganic CVD) Molecular Beam Epitaxy Ion Implantation Lithography ( optical, UV, X-ray, E-beam)

8 CMOS Construction

9 Self Alignment by Ion Implantation

10 Metallization IC metallization provides the ohmic contact with the semiconductor Multilayer constructions are often required due to adhesion requirement. Adhesion layers include Ti,Ti/W, Cr, Co Multi-level interconnects required for on-chip interconnection. 2-5 layers currently Metallizations must be capable of fine line fabrication ( currently.25 microns) and must be resistant to hillock formation, electromigration, etc) Size reduction increases need for high conductivity

11 Multilayer IC Metallization

12 SIA Roadmap for Chip Interconnections

13 SEM View of Multilayer IC Metallization

14 Passive Components Capacitors Ceramic Tantalum solid electrolytic aluminum electrolytic Resistors thick film chip power Magnetic devices inductors transformers

15 Recent changes Affecting Passive Components DOD Acquisition reform; abandonment of military specifications and associated audit and quality control functions World wide ISO9000 quality standards, increasing offshore competition Drive towards miniaturization, low power, high frequency applications Increases in automotive, communication and computer applications

16 Parallel-plate Capacitor

17 Capacitor Properties Capacitance and tolerance Voltage rating Equivalent series resistance(esr) and power loss Insulating resistance (leakage current) AC rating Capacitance stability with temperature and frequency

18 Principle Capacitor Types Ceramic chip capacitor dielectrics made from sintered ceramics, often barium titanate most widely used style: low cost, wide range of characteristics, small size, excellent high frequency properties Solid electrolyte tantalum capacitors high volumetric efficiency, good stability and high reliability leakage current, limited voltage range and polarity can be problems Aluminum electrolytic Metallized plastic capacitors

19 Ceramic Chip Capacitor Construction Consists of an inter-digitated set of ceramic dielectric layers with metal electrodes Dielectric is based on high K ferroelectric barium titanate (BaTiO 3 ) or paraelectric titanates for NPO dielectrics Electrodes are Ag or Ag/Pd alloys End terminations are thick film metallizations, which can be Ni plated to minimize solder leaching Value within a size range obtained by increasing the number of layers, as the dielectric thickness remains constant

20 Typical Ceramic Chip Capacitor Construction End Termination

21 Dielectric Properties

22 Deaging After undergoing the phase transformation at the Curie temperature, the effective dielectric constant will decrease with time due to domain relaxation. This is called deaging. For BX dielectrics, it is about 2%/decade hr. NPO does not deage because it is fabricated from a paraelectric dielectric

23 Barium Titanate Crystal Structure Cubic Perovskite Structure Tetragonal Structure Below the Curie Point

24 Temperature Coefficient of Capacitance The temperature response of BaTiO 3 can be modified by either adding materials that shift the Curie point (usually solid solutions perovskites) or suppress the dielectric response over temperature (depressors). Shifters Depressors

25 Size Configuration Size configuration ranges from 0402 to 2225, with 0201 currently being introduced. Due to size reduction constraints, the smaller sizes are preferred.the choice of dielectric (NPO, X7R, Z5U) allows a wide range of values to be obtained, based on electrical and reliability performance.

26 Tantalum Electrolytic Capacitors Solid electrolytic tantalum capacitors have the highest vales of capacitance per size for chip components The high capacitance is obtained by using a large area ( porous sintered powder) and a thin dielectric thickness ( tantalum oxide from 10 to 70 nanometers(.01 µm) The capacitors are polar-i.e. they have a positive and negative terminal and circuit polarity must be observed. Reverse operation can lead to dielectric breakdown and catastrophic failure

27 Solid Tantalum Electrolytic Capacitor Tantalum capacitor has an porous sintered tantalum anode body with an electrochemically formed tantalum oxide dielectric. The counter-electrode is made from a semiconducting film of manganese dioxide and colloidal graphite/silver epoxy coating

28 SMT Configurations for Tantalum Capacitors Molder SMT Configuration Hybrid tantalum chip capacitor

29 Sizes of Tantalum Capacitors per MIL-C For a given size, the value is changed by the thickness of the dielectric, and hence the voltage rating. Thus in size A, capacitors from the range 0.1 to 2.2 microfarads are available

30 Resistor Properties Resistance and tolerance Stability during operation Resistance stability with temperature and voltage Maximum working voltage Critical resistance value for a given voltage and power rating, the resistance value that would dissipate full rated power at rated voltage Noise

31 Chip Resistors Chip resistors are typically thick film resistors on an alumina substrate with wrap around end terminations or standard thick film inks ( Pd-Ag) Chip resistors come in the size configuration of chip capacitors, however, a single size covers all values and is determined by power. For size constrained applications, small sizes, such as 0504 or smaller, are utilized Chip resistors are also available in thin film, with lower TCRs, and in arrays.

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34 Chip Resistor

35 MELF Construction Metal Electrode face bonding (MELF) are a packaging configuration which is used for circular devices ( or devices which were previously leaded, with a circular body. This includes diodes, resistors, and capacitors

36 Magnetic Devices Classified by construction and use: Coil: conductor wound in helical or spherical shape to form an inductor Choke: simple coil that conducts DC, but impedes ac current due to inductance Core: magnetizable portion of a device Transformer: two inductively coupled wirewound coils, usually on a single core. Used to step-up or step-down voltage at the same ac frequency

37 Magnetic Properties DC resistance Inductance Permeability Quality factor: ratio of stored to dissipated energy per cycle Self resonant frequency Temperature rating Voltage rating, insulation resistance

38 Chip Inductor Cross-sectional view

39 Other Components Crystals, crystal oscillators Connectors Switches Fuses Relays

40 Application Considerations Derating Environmental Stresses temperature mechanical humidity EMI/RF others Attachment procedures Circuit considerations

41 Derating Operating components at electrical and environmental stress levels lower than the maximum rated to reduce failure rates Recommended factors ( fraction of maximum rated stress to be used) vary with part type, materials, and quality levels Summary table just supplies general information: detailed information needed for specific application

42 Derating Factors, Summary Part Derating Factor Stress Diodes Current, PIV Transistors 0.5 Power, Current ICs 0.8 Current, Voltage, Power Capacitor Voltage Resistor 0.5 Power Feedthru filters 0.7 Voltage,Current Switches 0.8 Current Transformers 0.4 Power Fuses 0.5 Output current

43 Packaging Trends Wider use of Multichip Modules (MCM) and multichip Packages (MCP) MCP s will have same footprint as single chip packages Migration from Perimeter I/O to area I/O Single chip package will migrate smaller to chip scale IC s will continue to follow Rent s Rule, with increases in I/O and memory doubling every 2.5 years

44 SAI Roadmap for ICs (1995)

45 SAI Roadmap

46 Packaging Trends

47 Component Density for Portable Electronics

48 First Level Assembly First level assembly interconnects the component to the next higher level of assembly, either a discrete package or directly to the interconnect structure as in direct chip attach (DCA) techniques First level attach includes ultrasonic aluminum and thermosonic gold wire bonding,tab (tape automated bonding) and soldering

49 Wire Bonding for First Level Interconnection

50 Aluminum Ultrasonic Wedge Bonding The aluminum wire (typically 1 mil, but ranges from.7 to 10 mils)is located between the tool and the material to be bonded The tool presses against the surface at a predetermined force and ultrasonic energy is applied in a lateral motion The tool is raised while the wire is played out from the spool The tool is placed over the second bond location, brought into contact and pressure and ultrasonic energy is applied A wire clamp closes and pulls on the wire, breaking it at the heel of the bond

51 Aluminum Ultrasonic Wedge Bonding

52 Al Wedge Bonding (Cont.)

53 Gold Thermosonic Ball Bonding Gold wire is feed through the capillary, and a electric discharge melts the wire into a ball at the tip The ball is positioned against the bottom of the capillary, lowered to the bonding pad on the device to be bonded, which is heated. Ultrasonic energy and pressure are applied The tool is raised with the wire able to slip through the capillary. The tool is positioned over the second bond The tool is lowered to produce the second bond (called a stitch bond) The tool is raised while the wire is clamped, causing the wire to break

54 Top and Side View of a Wedge Bond

55 Gold Thermosonic Ball Bonding

56 Gold Thermosonic Ball Bonding (Cont.)

57 Top and Side View of a Ball Bond

58 Gold Ball Bonds First bond Second bond

59 Ultrasonic Wedge Bonds First Bond Second bond

60 Spacing Limitations for Ball Bonding

61 Wire Bond Examples Staggered Bonds to Reduce Effective Pitch Examples of Fine-pitch Ball and Wedge Bonds

62 Tape Automated Bonding TAB was developed to allow simultaneous bonding of all chip bonds ( inner lead bonds) by thermocompression bonding TAB requires a gold bump on either the chip or the lead for the inner lead bond (ILB) The outer lead bond (OLB) is usually soldered but can be thermosonically bonded

63 TAB Construction, Prior to Excising the Chip

64 TAB Inner Lead Bonding

65 Bumping Options for TAB Bumped Chip Bumped Tape

66 Gold Bump Process

67 40 Lead Tab Tape Example Mesa Technology

68 Solder Assembly Another method of first level assembly is to create solder balls at the IC pad locations. Since solder does not wet aluminum, a multilayer metallization structure must be provided to provide adhesion and leach resistance ( example Cr, Ti, Ti-W) and easy wetting for the solder (Cu, Ni, Au) Solder could be added by plating or evaporation through a mask,

69 Flip Chip Assembly

70 Solder Bumping

71 Solder Bump

72 Solder Bump Metallizations Hitachi Honeywell-Bull

73 Single Chip Packaging Through Hole Packages Surface Mounted Packages

74 Molded Plastic Packages

75 Types of First Level Packages

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79 Through Hole Versus Surface Mount Assembly Technique Surface Mount Technology Through Hole Technology

80 Comparison of SMT and Thru-hole Component Sizes Passive Components Active Components

81 Ball Grid Array Packages

82 QFP-PBGA Size Comparison A comparison of the 208 lead QFP and the 208 lead PBGA demonstrates the size reduction in moving from peripheral to area array connections

83 High I/O Packages (PQFP/BGAs) PQFP are projected to dominate I/O counts up to 200, with 0.5mm lead pitch BGAs will dominate over 300 I/Os, due to small pitch (0.3mm) of equivalent PQFPs and area efficiencies of BGAs Although BGAs are projected to grow at 25%/year, only 2 billion BGAs are anticipated in use by 2004, compared to 23 billion PQFPs BGA availability up to 736 I/Os (TBGA)

84 BGA Formats Plastic overmolded (PBGA)-up to 400I/O Tape carrier (TBGA) -up to 736 I/O Ceramic (CBGA)-up to 625 I/O Ceramic Column (CCBGA)- over 1000 I/O Cavity BGA-up to 596 I/O Metal body (MBGA)

85 Plastic BGA

86 Plastic Ball Grid Array (PBGA)Package PWB laminate substrate, usually BT or similar Wire bonded or flip chip Cavity up or down Bulk of body is molding compound; can be combined with a heat sink.030 diameter solder balls, usually eutectic or Sn62 Typically 1.27 or 1.5 mm grid, mm body size Multiple manufactures ( Amkor, Motorola, IBM,

87 Ceramic Ball Grid Array (CBGA) Package Standard multilayer ceramic substrate Flip chip or wire bonded White or black ceramic Cavity up or down /10 Pb/Sn solder balls Typically 1.27 mm grid, 18 to 32 mm body size Balls attached with eutectic solder

88 CBGA

89 Tape Ball Grid Array (TBGA) Packages 2 metal layer( 1 ground, I signal) TAB type substrate Flip chip or TAB bonding 25 mil diameter 90/10 Pb/Sn solder balls. Balls attached by partial reflow to plated through holes of the TAB substrate A stiffner is attached to the outer-lead portion of the substrate. The entire package is epoxy encapsulated

90 TBGA

91 Various Ball Configurations

92 Chip Scale Packages (CSP) Currently over 50 CSP packages are available as: leadframe-based rigid substrate-based (PWB or ceramic) wafer level flex-circuit-based Flex producers can handle design rules of less than 65 µm pitch, allowing single metal layer routing

93 CSP Configurations

94 Tessera Compliant Chip CSP

95 Peripheral-Area Fan-in for Tessera µbga

96 Slightly Larger than IC (SLICC) Package

97 Tape Based CSPs Tape based CSP are the µbga (Tessera) and the flexbga µbga uses a face down die interconnected via TAB construction. Typically a fan-in approach flexbga is a fan-in/out technology. It is a face-up, flexbga is a fan-in/out technology. It is a face-up, wire bonded, overmolded structure on a single layer polyimide tape, similar to TAB tape

98 Ceramic CSP Multilayer alumina carrier with gold stud bumped die, mounted with conductive adhesive Matsushita

99 Die Size CSP (Shellcase)

100 Different CSP Constructions

101 Progression of Package Types

102 Package on Package (POP)

103 Stacked Die in Package

104 Multi-die in Package

105 Flex Stacked die Package

106 Comparison of µbga Versus Flip Chip

107 Underfilling Flip Chip

108 Underfill Encapsulants Provides strain relief for bumped solder connects by averaging load over entire layer, not only the bumps Must achieve low CTE with extremely low viscosities and high flow Dispensed along the edge of a preheated board to maximize flow Capillary action draws underfill under the chip Underfills are chemically tailored for the substrate material to accommodate different surface tensions

109 Effect of Underfill Prior to the introduction of underfilling, flip chip assembly on organic boards failed in thermal cycle after a few tens of cycles Using underfill, the same construction can survive over 5000 thermal cycles Underfill will allow flip chip DCA to become a dominant assembly method Underfill developments include methods where the encapsulant is applied prior to chip attach to minimize manufacturing time

110 Effect of Underfill on Temp Cycling Performance With filler, 27ppm

111 Reflow Encapsulation Underfill is applied prior to soldering Acts as adhesive prior to reflow Acts as a flux during soldering ( no clean) Cures as an encapsulant/underfill on exposure to the soldering temperature Minimizes post soldering operations

112 Kester Reflow Encapsulant

113 I/O Redistribution Type of Wafer-level CSP

114 Ball Formation- Electroplate Method

115 Paste Method for Ball Formation

116 Multi-chip CSP

117 Glob-top/Dam and Fill Encapsulation For direct chip attach, environmental protection must be provides Glob-top is the oldest,method to protect wirebonds, with controlled flow that allowed penetration between the wires and overmolding of the die in one step For fine pitch requirements, a more fluid encapsulation is desired to insure penetration of the wire bonds. In dam and fill, a dam is formed from a highly thixotropic encapsulant, followed by a fill of the highest possible flow encapsulant

118 Dam and Fill

119 SLC Process

120 Surface Laminar Circuit -SLC

121 Embedded Passives LTCC provides great promise for maximum product density with the ability to embed passive components within the LTCC substrate Currently, resistor, capacitors and inductors Currently, resistor, capacitors and inductors can be buried because of the materials compatibility of thick film materials and the multilayer construction

122 LTCC with Buried Components