tinyavr Microcontrollers White Paper is the registered trademark of Atmel Corporation, 2325 Orchard Parkway, San Jose, CA Rev.

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1 tinyavr Microcontrollers White Paper is the registered trademark of Atmel Corporation, 2325 Orchard Parkway, San Jose, CA R Rev.

2 Table of Contents Introduction to Microcontrollers... 1 Microcontroller Architectures... 1 Von-Neumann Architecture... 1 Harvard Architecture... 1 Issues for MCU Designs... 2 Atmel s tinyavr 8-bit Enhanced RISC MCU... 3 A Rich Set of Fixed-length 16-bit Instructions Developed for Highest Code Density... 4 Two Address Machine... 4 Single Cycle Instruction Execution... 4 Thirty-two 8-bit Registers... 5 Bit Manipulation Enhances Code Efficiency... 5 In-System Programmable Flash... 5 EEPROM for Calibration and Correlation Factors... 6 Analog-to-Digital Converter... 6 Timer/Counters... 6 tinyavr Development Tools... 6 ICE 10 and ICE 200 In-Circuit Emulator... 6 AVR Studio... 6 STK500 Starter Kit...7 Features... 7 Summary... 7 tinyavr Microcontrollers White Paper i

3 White Paper Introduction to Microcontrollers Microcontroller Architectures Von-Neumann Architecture Harvard Architecture CISC RISC Within the last 25 years microcontrollers have influenced the way we live. They can be found in keyless entry systems, car alarms, fire detectors and toys. They are used to achieve many different things from protocol conversion, battery charging to motor controls. For example, the average new automobile has microcontrollers that operate the brakes, airbag, suspension, fuel, engine emissions, temperature control, cruise control, window opener, windshield wiper and much more. The average PC uses ten microcontrollers, in addition to the system microprocessor. Altogether, the average US home has 130 microcontrollers that control everything from washing machines, dryers, dishwashers, and microwaves to telephones, stereo systems, garage openers, burglar alarms, thermostats and battery chargers. But let s start with a look at the different controller architectures that are available on the market. The MCU architectures can be divided in two categories: the Von-Neumann architecture and the Harvard architecture. Today, the most commonly used MCU architecture is the Von-Neumann architecture. These machines are characterized by having common shared buses and a single shared address space for both the data and program memories. Successful examples for this architecture include Motorola s 68HC05 and 68HC11 families of MCUs. All Von-Neumann machines have a bottleneck that hinders systems performance because they have just a single bus for both the address and data. This means that instructions and data cannot be fetched simultaneously. An instruction must be fetched during one clock cycle and the data must be fetched during the next. Operations that could be performed quickly must wait for these alternative program data cycles to complete. The Harvard architecture is gaining popularity in the MCU market. It eliminates the instruction bottleneck associated with Von-Neumann machines by providing separate buses for the data and address. This is achieved by using separate buses for addresses and data. It increases the throughput of the microcontroller significantly, up to single cycle execution of the instructions. Another way to distinguish between architectures is to divide them into CISC and RISC machines. The Complex Instruction Set Computers (CISC) machines were designed to perform complex operations with one instruction, thus reducing the number of instructions required to perform a given task. In most cases, this makes CISC machines very code efficient. However, the complex instruction set requires complex hardware logic and also multiple clock cycles per instruction. This tends to make them relatively expensive and slow. A CISC machine can require more than 20 clock cycles to execute a single instruction. Also called Reduced Instruction Set Computers (RISC) machines, these microcontrollers have simple fixed-length instructions that can be executed in fewer clock cycles than a CISC machine. The term Reduced means that the complexity of each instruction is reduced. Typically, the instruction set is limited to perform simple arithmetic operations on a set of data registers and transferring data between these registers and the data memory. The simple instruction allows single cycle execution, which greatly increases execution speed. The hardware logic required to handle a RISC instruction set is simpler than that of a CISC machine, enabling a significant cost reduction. The drawback traditionally associated with RISC architectures is that they tend to require a 1

4 larger number of these simple instructions to perform a given task, increasing the amount of the memory required to house the program. Issues for MCU Designs Increased Performance Power Consumption Issues Shorter Product Life Cycles 2 White Paper The main issues to be addressed when specifying a microcontroller are cost and performance. Performance will be a function of the microcontroller architecture (CISC or RISC), its utilization of pipelining, its instruction set, its support for C-compilers, its buswidth and its clock frequency. Faster and wider microcontroller buses tend to offer better performance, but they are also much more expensive. Conversely, low system cost is often associated with the use of less expensive, 8-bit devices that also offer poor system performance. Thus, it seems that low cost and high performance are mutually exclusive phenomena. This need not be the case. High system performance can be achieved without radically increasing system costs by taking advantage of new architectural innovations provided by Atmel s AVR family of microcontrollers. A combination of factors contribute to the total cost of a microcontroller, which include the amount of memory required for program storage, the need and facilities to modify designs to correct errors or add features, system performance goals and how many additional parts are necessary to achieve the required functionality. Having additional parts on the PCB make the PCB and the assembly of it much more expensive. Therefore the price of the microcontroller is only one factor that contributes to the overall system cost. The tinyavr microcontroller provides high performance, substantial on- MCU program store, In-System Programmability (ISP), and a variety of on-mcu peripheral functions. There are several approaches to achieving better throughput. One approach is to use a wider bus and/or a faster clock, but these approaches tend to be very expensive. Since system power consumption increases proportionately to clock speed, increasing the clock will increase the power consumption. Therefore more economical means of increasing microcontroller throughput is to modify the microcontroller architecture to eliminate bottlenecks and to increase its ability to handle multiple instructions at once. This will also allow the designer to minimize fetch and store operations and to minimize the number of instructions it must execute to get a job done. This approach increases the performance without having an impact on the next point, which is very important for most of the design especially for battery powered systems. Wireless and other portable products are proliferating at a rapid rate. Battery powered systems require power consumption to be minimized in order to keep battery size, product weight and cost down, and to extend battery life. Integrating the program and data memory as well as many additional peripherals integrated not only reduces the product size, but also decreases the power consumption. In fact, the extra ICs associated with using off-mcu NVM can increase the power consumption by a factor of six, compared with an on-chip NVM. This is because the most power-hungry transistors are those that drive inter-chip interfaces. With a high performance controller, the best way to reduce power consumption is to use the sleep and power down modes. If a certain task can be accomplished in half the time, when compared with another controller, the faster MCU can enter into sleep mode for half the time, and wake up for the next task. This is the most efficient way to reduce power consumption even more than can be achieved by only reducing the clock frequency. Competitive pressures have sliced some product life cycles to as little as six months. Generally, product enhancements are made in the firmware, so the code is continuously evolving. EPROM or OTP MCUs which must be programmed prior to product assembly are often replaced with enhanced versions before their inventory is used up. In addition, multiple OTP MCUs with different code must be kept in inventory to accommodate dif-

5 White Paper ferent products that use the same hardware design, but are differentiated using firmware. The difficulties often associated with forecasting demand often result in excessive inventory that must be discarded when the new generation product is introduced. All excess unusable inventory adds to the effective product cost. A significant saving comes from In-System Programmable on-chip NVM. The ability to carry only inventory of non-programmed parts makes product changes much easier when programming a different firmware or a different country or product version, simply by downloading a new hex file. Easy Field Updates Atmel s tinyavr 8-bit Enhanced RISC MCU Rapid changes in our environment make field updates necessary for many applications. The possibility to update a microcontroller via a telephone line, RS232 or even via the Internet makes field updates possible without sending a service person to the location itself. Eliminating field service calls can save far more than the cost of the original equipment. In summary, many existing microcontroller architectures are no longer suitable for today s system requirements of fast instruction execution, lower power consumption or In-System programming requirements. Atmel s family of tinyavr microcontrollers comprise a reduced instruction set (RISC) machine, employing a true Harvard architecture with separate busses and address spaces for program and data memories, load and store operation, 32 8-bit registers and single-cycle instruction execution. The RISC architecture was selected because it eliminates the bottleneck and performance penalty associated with accumulator-based CISC architectures, in which, program and data share the same bus where several complex multi-clock instructions are required to complete virtually any operation. In developing its tinyavr family, Atmel has taken the Harvard architecture and added several enhancements that allow it to provide exceptional performance, sufficient In-System Program store to accommodate the largest applications, excellent code density, and on-chip peripherals that meet the needs of today s advanced sensor-based systems. These enhancements include: 16-bit fixed-length instructions to increase code density by eliminating the need for logic to determine instruction length Up to 118 instructions that have been optimized so that approximately 80% of all MCU operations can be handled by a single cycle instruction 8-bit register files that allow the CPU to access multiple data simultaneously, eliminating the need for most data transfer operations, thereby enabling much smaller code size 1 to 2 kilobytes In-System Programmable Flash memory for program code storage Integrated EEPROM with over 100,000 guaranteed erase/write cycles to accommodate and update constants, algorithms, and calibration data Low-power idle, noise reduction and power-down modes Programmable lock bits to protect Flash memory from being read to prevent reverse engineering Operation voltage range of 1.8V 5.5V Programmable brown out detection Wide selection of programmable peripherals that includes integrated RC Oscillator; PLL for fast PWMs; timer/counters with prescaler and pulse width modulation; programmable watchdog timer with on-chip oscillator; analog comparator and 10-bit ADCs 3

6 A Rich Set of Fixedlength 16-bit Instructions Developed for Highest Code Density Two Address Machine Single Cycle Instruction Execution The tinyavr instruction set consists of up to 118 fixed-length 16-bit instructions that eliminate the need for logic to determine instruction length, contributing to higher code density. More importantly, the instruction set was developed based on actual code implementations. Atmel evaluated numerous existing designs, and identified the most frequently used individual instructions, as well as the most frequently used instruction combinations. tinyavr instructions were developed to directly support 90% of the operations most commonly used in MCU designs in just one instruction. Individual instructions are included that implement frequently used combinations of operations. For example, the comparison of 16- or 32-bit numbers is an extremely common operation particularly in C-code. Implementing a 16-bit comparison in most 8-bit machines typically requires ten instructions and 132 clock cycles to subtract the low byte, test, jump up, carry, continue with the high byte, test again, and propagate the zero flag to the high byte. The tinyavr instruction set provides two instructions (subtract with carry and compare with carry) that execute the entire operation in four clocks at most, including the propagation of the carry and zero flags. The C-compiler compiles the instruction directly from the C-code. To eliminate the need for carry instructions with constants during a 16-bit ADD, Atmel implemented the ADD instruction as subtract and carry instruction (SBCI). This enables 16- and 32-bit arithmetic with no code size penalty for 8-bit arithmetic. The compare with carry instruction enables non-destructive comparison of numbers that are greater than 8 bits. This common-sense approach of implementing the most frequently used functions in individual tinyavr instructions results in exceptionally dense compiled code. In a competitive analysis of code density for a variety of applications running on several popular MCU architectures, the tinyavr consistently had the highest code density. Even the highly respected 16-bit H8/300 required 20% more code than the tinyavr to implement the same functionality. Eight-bit MCUs such as the 80C51 and Microchip s PIC required 45% to 65% more code. Two addresses enable the 8-bit tinyavr to simultaneously load and store the entire 16-bit instruction. It also facilitates comparisons of 16- and 32-bit numbers. A pair of two 8-bit registers can be added or subtracted directly using the two-addresses. Although other 8-bit Harvard-based microcontrollers require many fewer cycles per instruction than CISC machines, only rarely do they execute in a single cycle; three or four cycles per instruction is more common. The tinyavr has achieved true single cycle execution by implementing a two-stage pipeline in which the next instruction is fetched while the current instruction is executed. ALU operations and branches execute in a single instruction. Loads, stores and taken branches execute in just two cycles, while the slowest instruction, RET, takes only four clocks. Across a wide spectrum of applications, the tinyavr averages 1.3 instructions per clock cycle twice as much throughput as its nearest competitor, the H8/300, and over ten times more throughput than the 80C51. The tinyavr can execute up to 8 million instructions per second, with a maximum clock frequency of 8 MHz. Also, the superlative performance of the tinyavr enables it to meet or exceed the performance of many 16-bit MCUs at a fraction of the cost. 4 White Paper

7 White Paper Thirty-two 8-bit Registers Bit Manipulation Enhances Code Efficiency In-System Programmable Flash Most programmers would agree: you can t have too many data registers. Data registers greatly speed up instruction execution. However, very few 8-bit microcontrollers contain more than one or two registers. When most 8-bit architectures were developed in the 1970 s and 1980 s process technologies were much larger. The large silicon area required to implement data registers makes them too costly. Since then, process technologies have shrunk dramatically, greatly reducing the cost disadvantage. Adding registers eliminates the need to continuously transfer data in and out of the single accumulator in a CISC machine. Atmel has used today s small process technology to equip the tinyavr with thirty-two registers the maximum number of registers consistent with a 16-bit instruction. Sixty-four registers would have increased the two address decode instructions by 1-bit each, leaving only four bits for the operating code, and requiring longer instructions. Since this option would have decreased the code density, thirty-two registers were considered to be the optimum. The 32 8-bit registers in the tinyavr give the CPU access to multiple data simultaneously. They also greatly facilitate 16- and 32- bit arithmetic by allowing direct operations on them without having to load and operate on them in 8-bit segments. The tinyavr architecture and C-compiler support bit manipulation that further enhances code efficiency and security. Transfer Bit For example, scrambling data, as is typically done by a cable TV company to prevent unauthorized viewing of cable channels, can require six to eight instructions per byte. Given the number of bytes of data in your average TV show, this can lead to a massive number of instructions to execute. A very fast clock may be necessary to achieve the required performance. The tinyavr architecture greatly simplifies this process by providing a status register with a transfer bit. Any bit in the register file can be arbitrarily switched into the transfer register for scrambling and then transferred back for de-scrambling. This reduces an 8-instruction operation to a simple two instruction (load bit, store bit) operation. I/O-pin Bit Manipulation Individual I/O pins are frequently used to switch external devices, such as lights, door locks, or process machinery on or off. Most microcontrollers must read all the bits on the I/O port, change the appropriate bit, and then write them all back out to the port. In addition to requiring at least three instructions to execute this operation, it can result in the accidental, incorrect setting of other pins that could lead to catastrophic system failure. The tinyavr allows a single I/O bit to be directly and immediately set by a single instruction, without affecting any other I/O pin on the port. The In-System Programmability of the tinyavr cuts inventory costs by allowing various revisions of the code to be programmed at the end of the manufacturing process. The majority of microcontrollers have one-time-programmable (OTP) or EPROM program memory that must be programmed in special equipment before the controller is soldered in the final product. When the same hardware design is being used to implement multiple products that are differentiated by their firmware, large OTP MCU inventories must be maintained that have been programmed with different code. This situation is error prone and often results in the wrong OTP MCU being inserted in a product that consequently performs improperly in the field. Any bugs that are discovered will necessitate that all existing programmed OTP parts are thrown away, at great cost to the manufacturer. Finally, the inability to accurately forecast demand can result in inventory waste. The In-System Programmability of the tinyavr family of microcontrollers eliminates this needless waste by enabling system updates in the field, as well as on the factory floor. Code revisions or enhancements, as well as changes in product demand, are easily accommodated via the three-pin serial peripheral interface (SPI). Products can be reconfigured without disassembly. 5

8 EEPROM for Calibration and Correlation Factors Analog-to-Digital Converter Timer/Counters tinyavr Development Tools ICE 10 and ICE 200 In- Circuit Emulator AVR Studio Many embedded systems, such as ABS breaking systems are self-calibrating. As the system wears or operating conditions change new calibration data or correlation factors must be loaded. Atmel s tinyavr family provides a range of densities of In-System Programmable, byte-erasable EEPROM that allows calibration data and correlation factors to be updated as needed using the tinyavr serial peripheral interface. System data can even be updated remotely via telephone lines. The ISP features of the tinyavr even enable systems to self calibrate, measuring system conditions and revising calibration automatically. Information gathered by sensors, such as temperature, speed, humidity, acceleration, or light, is analog in nature. Analog data must be digitized into values represented by 0s or 1s before a processor can operate them on. Many microcontroller-based applications rely on analog data for their operation. For example, a fuel injection system, which must determine the fuel mix based on a variety of analog data such as temperature, revolutions per minute, and timing, must convert all this data to a digital form prior to performing algorithms that will determine the fuel mix. Some derivatives of the tinyavr family provide a built-in 4- to 11-channel 10-bit A/D converter to perform this function. It can operate in single-conversion mode, which is activated by the user, or in free-running mode, in which, the ADC constantly samples and updates the ADC register. The AD converter on tinyavr microcontrollers enables them to operate as a single chip solution in a myriad of applications that must sample and operate on analog data. Most tinyavr family members have prescaled timer/counters. tinyavr MCUs have 8-bit prescaler timer/counters. The timer counters enable the microcontroller to keep track of the number of times an operation has been performed or the amount of time that has elapsed. The tinyavr microcontroller family comes with a comprehensive set of development tools that include integrated development environment with assembler and simulator, In- Circuit emulators ICE10 and ICE200, and the STK500 starter kit. The ICE 200 is a real time in-circuit emulator (ICE) with an unlimited number of breakpoints that connects to the RS-232 port of any PC or workstation. The ICE10 supports all tinyavr parts with analog capabilities. All Atmel emulators are designed to work with the Integrated Development Environment, the AVR Studio, which automatically senses its presence. All Atmel AVR emulators can be purchased from any Atmel distributor. Further information on software and hardware support can be found on Atmel s web site. There is a huge section that lists all of Atmel s business partners that offer many items, from real-time operation systems to programming adapters. The AVR Studio Integrated Development Environment enables the assembling, execution and debugging of AVR programs using either the in-circuit emulator or using the AVR Studio's built-in Instruction Set Simulator. AVR Studio provides a Source window with the program code and a pointer that marks the code currently being executed. Other windows that are available include: Watch window that displays the values of defined symbols, allows direct manipulation of the data; Register window that displays the contents of all 32 registers; Memory window that allows the user the to view and modify the contents of all the memory resources; 6 White Paper

9 White Paper Processor window that shows the address of the next instruction to be executed, the value of the stack pointer, and the number of clock cycles that have elapsed since the last reset; Peripheral device windows, each of which shows the status of the I/Os; Port windows that show the three I/O registers on each of the ports on the AVR. Since version 4.0 of the AVR Studio the programming interface for the STK500 starter kit is integrated in the software. The AVR Studio development software is available free of charge on Atmel's web site, STK500 Starter Kit The STK500 starter kit is the most complete starter kit for any microcontroller: A professional starter kit and development system for the AVR Flash Microcontroller from Atmel. It is designed to give designers a quick start to develop code on the AVR, combined with advanced features for using the starter kit to prototypes and testing of new designs. The STK500 starter kit interfaces with AVR Studio, Atmel's Integrated Development Environment (IDE) for professional code writing and debugging. Features Compatible with AVR Studio V3.2 and newer RS232 Interface to PC for Programming and Control Regulated Power Supply for 10V 15V DC Power Sockets for 8-, 20-, 28-, and 40-pin AVR Parts Parallel and Serial High-voltage Programming of AVR Parts Serial In-System Programming (ISP) of AVR Parts In-System Programmer for Programming AVR Parts in External Target System 8 Push-Buttons and 8 LEDs for General Use All AVR I/O Ports Easily Accessible Through Pin Header Connectors Additional RS232 Port for General Use Expansion Connectors for Plug-In Modules and Prototype Area On-board 2-Mbit Data Flash for Non-Volatile Data Storage Software Upgradeable from AVR Studio to support future AVR parts Summary Atmel's 8-bit tinyavr family represents a single-chip solution for many different applications from battery charger, universal remote control to remote keyless entries. It combines the most advantageous attributes of CISC and RISC MCUs into a flexible, 8-bit machine that meets, sometimes exceeds the performance of many more expensive 16-bit machines. The tinyavr family consists of devices with 8 to 32 pins and onchip program memory ranges from 1 to 2 kilobytes of ISP Flash memory. Selected devices also have integrated EEPROM. With a wide variety of programmable peripherals there is certain to be one member of the tinyavr family available to provide a perfect solution for virtually any microcontroller application. Finally, the true Harvard architecture and single cycle instruction execution deliver performance that vastly exceeds that of any other 8-bit MCU available today at a sub one dollar price. 7

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