(51) Int Cl.: H05K 1/02 ( )

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1 (19) TEPZZ 4 67B_T (11) EP B1 (12) EUROPEAN PATENT SPECIFICATION (4) Date of publication and mention of the grant of the patent: Bulletin 13/12 (21) Application number: (22) Date of filing: (1) Int Cl.: H0K 1/02 (06.01) (86) International application number: PCT/US08/ (87) International publication number: WO 09/0888 ( Gazette 09/29) (4) METHOD FOR ARRANGING VOLTAGE SUPPLY PLANES IN A PRINTED CIRCUIT BOARD TO WHICH IS ATTACHED A SEMICONDUCTOR DEVICE FOR REDUCTION OF JITTER AND PCB HAVING SUCH AN ARRANGEMENT VERFAHREN ZUM STAPELN VON SPANNUNGSVERSORGUNGSEBENEN IN EINER MIT EINER HALBLEITERVORRICHTUNG BESTÜCKTEN LEITERPLATTE ZUR JITTER-REDUKTION UND LEITERPLATTE MIT SOLCH EINEM STAPEL MÉTHODE D ARRANGEMENT DE PLANS D ALIMENTATION EN TENSION DANS UNE CARTE À CIRCUIT IMPRIMÉ MUNIE D UN DISPOSITIF À SEMI-CONDUCTEUR POUR LA RÉDUCTION D INSTABILITÉS ET CIRCUIT IMPRIMÉ COMPRENANT UN TEL ARRANGEMENT (84) Designated Contracting States: AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MT NL NO PL PT RO SE SI SK TR (30) Priority: US 833 (43) Date of publication of application:.. Bulletin /42 (73) Proprietor: Xilinx, Inc. San Jose, California 9124 (US) (72) Inventor: DUONG, Anthony, T. San Jose, CA 9124 (US) (74) Representative: Naismith, Robert Stewart et al Marks & Clerk LLP Aurora 1 Bothwell Street Glasgow G2 7JS (GB) (6) References cited: US-A US-B EP B1 Note: Within nine months of the publication of the mention of the grant of the European patent in the European Patent Bulletin, any person may give notice to the European Patent Office of opposition to that patent, in accordance with the Implementing Regulations. Notice of opposition shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention). Printed by Jouve, 7001 PARIS (FR)

2 Description FIELD OF THE INVENTION [0001] The present invention relates to printed circuit boards (PCBs) and package substrates, and more particularly to the reduction of jitter in a semiconductor device by controlling stackup. BACKGROUND OF THE INVENTION [0002] Programmable logic devices (PLDs) are a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, programmable input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAMs), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth. Notably, as used herein, "include" and "including" mean including without limitation. [0003] One such FPGA is the Xilinx Virtex FPGA available from Xilinx, Inc. of San Jose, California A FPGA typically includes an array of CLBs surrounded by a ring of IOBs. The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration data may be read from an external memory, conventionally an external integrated circuit memory EEPROM, EPROM, PROM, or the like, though a computer may also be used to provide the data. The collective states of the individual memory cells then determine the function of the FPGA. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a "processor block." The FPGA is attached to a printed circuit board (PCB) of a computer or other similar device. [0004] Another type of PLD is the complex programmable logic device (CPLD). A CPLD includes two or more "function blocks" connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure. For purposes of clarity, FPGAs are described below though other types of PLDs and semiconductor devices may be used. [000] Fig. 1 shows an example printed circuit board (PCB) 0 having mounted thereon an example FPGA chip. A plurality of contact members, for example metal pad regions or pogo pins (not shown), extend from the upper surface of PCB 0. The FPGA chip has mounted thereon a plurality of solder balls 1 for electrically connecting to the contact members of the PCB 0. The FPGA chip also includes die 1 electrically connected to a carrier via bumps 1. PCB 0 includes layers for power supply voltage rails, ground and signal lines (not shown). Vias connect these layers through solder balls 1 to and through the circuitry of the FPGA. [0006] PCBs can contribute to jitter in FPGAs resulting from connections to the PCB layers while the PCB voltage supply drives circuitry of the FPGA. One factor contributing to jitter is local voltage supply noise in the PCB. Parasitic inductive, capacitive, and resistive loads along the lines supplying power and signals to elements in the FPGA can cause voltage fluctuations, including ground bounce and supply bounce, which increases local power supply noise in the PCB. This noise provided to delay elements creates jitter in the FPGA on a clock signal containing the delay elements. [0007] Fig. 2 shows a current example stackup for a twenty-four-layer PCB. This PCB 0 has three power supply planes 11, 13 and 14 and ten signal planes 1, 3,, 7, 9, 16, 18,, 22 and 24. This implementation places all the power supply planes 11, 13, and 14 in the middle of the board, without any particular rules assigned as to what order each power supply plane appears within the stackup. For example, the power supply planes can be differentiated due to their different voltages. As another example, some "core" power supply planes power timing-critical circuitry within the FPGA, whereas other power supply planes power input/output circuitry within the FPGA. Further, this stackup has two power supply planes 13 and 14 that are adjacent to each other, which allows noise from one plane to couple onto the other. [0008] Fig. 3 shows a current example stackup for an eight-layer package substrate 300. The package substrate 300 is a PCB-like structure used to mount a silicon die. A die 3 is electrically connected to the package substrate 300 through conductive balls 3. Of note, the primary core supply, shown as "Vcc - Primary Core Supply Plane" on plane 6, and secondary core supply, shown as "Vcc - Secondary Core Supply plane" on plane 7, are farther away from die 3 than the I/O power supply, shown as "Vcc - I/O Supply Plane on plane 4." [0009] Fig. 4 shows a current example stackup for a ten-layer package substrate 300. Of note, the primary core power supply, shown as "Vcc - Primary Core Supply Plane" on plane 6 is farther away from die 3 than the first I/O power supply, shown as "Vcc - I/O Supply Plane" on plane 4. Similarly, the secondary core supply, shown as "Vcc - Secondary Core Supply Plane" on plane, is farther away from the die 3 than both the first and second I/O power supply planes, shown as "Vcc - I/O Supply Plane" on planes 4 and 8. [00] US61804 describes a printed circuit module that supports host processors and memories. The module 2

3 includes a multilayer printed circuit board with a symmetrical design, permitting chips to be placed on both sides of the board. Microvias connect the contact points on a signal layer directly to a ground layer on the printed circuit board, thereby reducing the need for escape routing. This greatly simplifies the design layout of the module. The ground layer is located between two signal layers, thereby decreasing the crosstalk between the signal layers. The symmetrical design permits drilled vias to extend from a quadrant of one chip and exit through a similar quadrant on the opposite side of the circuit board. [0011] US0229 describes a printed circuit board that includes a power plane and a ground reference plane that includes two opposite sides. The power plane is positioned proximate one side of the ground reference plane. A signal layer is positioned proximate the other side of the ground reference plane to isolate the power plane from the signal layer. Any noise on the power plane or the signal layer is thus isolated by the intervening ground plane. [0012] It is desirable to reduce the amount of jitter on a clock as it propagates through a PCB to and through a silicon device, such as a FPGA. SUMMARY OF THE INVENTION [0013] Various aspects of the invention are defined in the independent claims. Some preferred features are defined in the dependent claims. [0014] A model and method are described herein for lowering device jitter by controlling the stackup of PCB planes so as to minimize inductance between a FPGA and PCB voltage planes for critical core voltages within the FPGA. Furthermore, a model and method are described herein for lowering jitter by controlling the stackup of package substrate planes so as to minimize inductance between a die and substrate voltage planes for critical core voltages within the die. BRIEF DESCRIPTION OF THE DRAWINGS 2 [00] Further details of the present invention are explained with the help of the attached drawings in which: Fig. 1 shows an example PCB having mounted thereon an example FPGA; Fig. 2 shows a current example stackup for a twenty-four-layer PCB; Fig. 3 shows a current example stackup for an eight-layer package substrate; Fig. 4 shows a current example stackup for a ten-layer package substrate; Fig. shows an example controlled stackup for a twenty-four-layer PCB, according to embodiments of the present invention; Fig. 6 shows an example controlled stackup for a twenty-two-layer PCB, according to embodiments of the present invention; Fig. 7 shows an example controlled stackup for a twenty-layer PCB, according to embodiments of the present invention; Fig. 8 shows an example controlled stackup for an eight-layer package substrate, according to embodiments of the present invention; Fig. 9 shows an example controlled stackup for a ten-layer package substrate, according to embodiments of the present invention; and Fig. shows an alternate example controlled stackup for a ten-layer package substrate, according to embodiments of the present invention. 4 0 DETAILED DESCRIPTION [0016] Various embodiments of the present invention provide for reducing the amount of jitter on a clock as it propagates through a PCB to and through a silicon device, such as a FPGA. Jitter can be suppressed by minimizing the amount of ripple, both peak-to-peak amplitude and oscillation, present on the internal voltage rails that drive timing-critical circuitry on the FPGA. These voltage rails run through planes of the PCB to and through the FPGA. Examples of a FPGA s timing-critical circuitry are clock trees, delay lines, and digital clock management (DCM). These circuits operate on the primary core voltage. A clock tree distributes the system clock signal from a common point to all the elements of the system using the clock signal. A delay line is a transmission line or equivalent device, such as an analog delay line, used to delay a propagating signal. A delay line as described herein can also include a physical device such as a buffer used to provide a controlled delay between clock pulses. Delay lines can be used to synchronize clock signals used to clock various circuits. For example, delay lines may be used in a wide variety of digital clock management (DCM) circuits to adjust the skew between input and output clock signals. [0017] Circuitry that operates on the secondary core voltage includes, but is not limited to, internal voltage regulators, band-gap, and bias voltages. Some small portions of the delay line and DCM circuitry also operate on this supply. 3

4 [0018] Circuitry that operates on the Input/Output (I/O) supplies includes input receivers and output drivers. The I/O supplies do not source any of the core circuitry such as clock trees, delay lines, or digital clock management (DCM). [0019] Jitter is reduced by minimizing the amount of ripple and transient noise present on the voltage rails that drive timing-critical circuitry on the FPGA. In order to reduce noise on these voltage rails, inductance on these voltage rails must be reduced. In other words, the inductance between the FPGA and the voltage planes of the PCB for critical core voltages supplied to the FPGA must be reduced. The initial transient voltage caused by inductance on lines carrying voltages from power supply planes is governed by the following Eqn. 1: V L = inductor voltage L = inductance, and i = current. [00] From this equation, V L can be reduced by minimizing L. This is achieved by controlling the depth from the solder ball of the FPGA package to the supply planes on the PCB, which is governed by the following Eqn. 2: 2 d = the length from the ball to the plane and v = the diameter of the break-out via [0021] Since the equation for L is dictated primarily by d, it is imperative to control d to achieve optimal L. In semiconductor devices such as a FPGA, certain circuits are timing sensitive such that their performance and propagation hinge largely on the root-mean-square (RMS) voltage level and transient fluctuations that are present on the internal supply. By maintaining the RMS level and minimizing the transient fluctuations, the variability in delay of such circuit is reduced. Hence, jitter performance is enhanced by minimizing d. [0022] Fig. shows an example controlled stackup of a twenty-four-layer PCB, according to embodiments of the present invention. PCB 0 is shown as having twenty-four different planes, labeled one through twenty-four. PCB 0 has ten signal planes. PCB 0 also has five supply planes, two more than the current twenty-four layer stackup shown in Fig. 2. The stackup of the planes of the PCB 0 is properly constrained to minimize the amount of jitter on a clock as it propagates to a FPGA from the PCB 0. The FPGA has solder balls 1 mounted thereon and is the same FPGA as shown in Fig. 1. In embodiments described herein, devices other than FPGAs can be used including but not limited to other types of PLDs and other semiconductor devices. [0023] In Fig., the power, signal, and ground planes of the PCB 0 are connected to the FPGA through power, signal, and ground lines that extend as vias from the PCB planes through the solder balls 1 to the circuitry of the FPGA. Conductive lines and vias making up power, signal, and ground lines include the power, signal, and ground planes. Only some of the power, signal, and ground planes are shown in Fig. for clarity. For example, ground planes 2 and 4 are connected to the FPGA through ground lines 140 and 160, respectively. Core supply planes 3 and 8 are connected to the FPGA through power lines 0 and 180, respectively. Signal planes 1 and are connected to the FPGA through signal lines 130 and 170, respectively. [0024] Regarding stackup of PCB planes, the following design rules apply. [002] First, all core supply planes are closer to the FPGA than all I/O supply planes. [0026] Next, as discussed above, the core supply planes are stacked in a particular order so as to minimize d, the length from the ball to particular ones of these core supply planes 3, and 8. The primary core supply voltage from the PCB that sources all timing-critical circuitry within the FPGA should be put on the voltage supply plane of the PCB that is closest to the FPGA. This minimizes d, the length from the ball 1 to the plane. The primary core supply voltage is shown as "Vcc - Primary Core Supply Plane" on plane 3. [0027] The secondary core supply voltage from the PCB should be placed on the next available voltage supply plane of the PCB, followed by the tertiary core supply voltage, and so on. The example PCB 0 has a secondary and final core supply voltage, shown as "Vcc - Secondary Core Supply Plane" on plane 8. The example PCB 0 does not have any tertiary or other core supply voltages. In embodiments, PCB 0 can have one or more core supply planes. [0028] Next, supply voltages from the PCB that drive strictly input/output (I/O) circuitry within the FPGA, and have no 4

5 impact on the operation of timing-sensitive circuitry of the FPGA, should be placed on voltage supply planes of the PCB farther away from the FPGA. The supply with the largest voltage on the PCB should be placed farthest away from the FPGA. Because I/O standards sourced by larger supply voltages generally have more margin for noise, they can tolerate larger voltage fluctuations. [0029] Three I/O supply planes are shown. The I/O supply plane supplying the largest voltage to FPGA is farthest from the FPGA, and is shown as "Vcc - Highest Voltage I/O Supply Plane" on plane 22. The I/O supply plane supplying the next largest voltage to FPGA, is second farthest from the FPGA, and is shown as "Vcc - Higher Voltage I/O Supply Plane" on plane 17. The I/O supply plane supplying the lowest voltage to FPGA is closest to the FPGA of the I/O supply planes, and is shown as "Vcc - Lowest Voltage I/O Supply Plane" on plane 13. In embodiments, PCB 0 can have one or more I/O supply planes. [0030] Next, each of the supply planes 3, 8, 13, 17, and 22 is associated with at least one ground plane, as illustrated in Fig.. For example, supply plane 13 is associated with one ground plane 12, while the four supply planes 3, 8, 17, and 22 are associated with two ground planes 2 and 4, 7 and 8, 16 and 18, as well as 21 and 23, respectively. [0031] Another rule for a controlled PCB stackup is that the second to last layer is a ground plane and the third to last layer is an I/O supply plane. In Fig., for example, the second to last layer is ground plane 23, and the third to last layer is "Vcc - Highest Voltage I/O Supply Plane" on plane 22. [0032] Fig. 6 shows an example controlled stackup for a twenty-two-layer PCB, according to embodiments of the present invention. There are five supply planes and ten signal planes as in Fig.. The number of planes, however, has been reduced by two ground planes. The rules as described above for Fig. are used, and Fig. is used as a starting point in order to reduce two ground planes. In Fig. 6, three supply planes 8, 12, and 16 are associated with one ground plane 7, 11, and, respectively. The two supply planes 3 and are still associated with two ground planes 2 and 4, as well as 19 and 21, respectively. [0033] Fig. 7 shows an example controlled stackup for a twenty-layer PCB, according to embodiments of the present invention. There are five supply planes and ten signal planes as in Fig. 6. However, the number of planes has been reduced further by two ground planes. Thus, in Fig. 7, all five supply planes 3, 7, 11, and 18 are associated with one ground plane 2, 6,, 14, and 19, respectively. [0034] Fig. 8 shows an example controlled stackup for an eight-layer package substrate, according to embodiments of the present invention. A package substrate is a PCB-like structure used to mount a silicon die. One implementation shown in Fig. 8 shows that the main primary core supply plane, shown as "Vcc - Primary Core Supply Plane" on plane 3 is placed on the supply plane closest to a die (not shown). In addition, "Vcc - Primary Core Supply Plane" can be placed in part on plane 1 in portions not used for routing signals. Bringing the primary core supply plane to plane 1 further reduces inductance to the die. Further, both core supply planes, shown as "Vcc - Primary Core Supply Plane" on plane 3 and "Vcc - Secondary Core Supply Plane" on plane, are closer to the die than any I/O supply planes. In this implementation, there is only one I/O supply plane, shown as "Vcc - I/O Supply Plane" on plane 7. [003] Fig. 9 shows an example controlled stackup for a ten-layer package substrate, according to embodiments of the present invention. The main primary core supply plane, shown as "Vcc - Primary Core Supply Plane" on plane 3 is placed on the supply plane closest to a die (not shown). In addition, "Vcc - Primary Core Supply Plane" can be placed in part on plane 1 in portions not used for routing signals. Bringing the primary core supply plane to plane 1 further reduces inductance to the die. Further, both core supply planes, shown as "Vcc - Primary Core Supply Plane" on plane 3 and "Vcc - Secondary Core Supply Plane" on plane, are closer to the die than any I/O supply planes. In this implementation, there are two I/O supply planes. The lowest voltage I/O supply plane, shown as "Vcc - Lowest Voltage I/O Supply Plane" on plane 7, is closest to the die of the I/O supply planes. Finally, the highest voltage I/O supply plane, shown as "Vcc - Higher Voltage I/O Supply Plane" on plane 9, is farthest from the die. [0036] Fig. shows an alternate example controlled stackup for a ten-layer package substrate, according to embodiments of the present invention. The stackup in Fig. is similar to Fig. 9 except that the order of "VCC - Higher Voltage I/O Supply Plane" and the adjacent ground plane on planes 8 and 9 has been swapped. [0037] Although the present invention has been described above with particularity, this was merely to teach one of ordinary skill in the art how to make and use the invention. Although Fig. shows two signal layers adjacent to each power/ground sandwich, other embodiments can have one or zero signal layers. Many additional modifications will fall within the scope of the invention, as that scope is defined by the following claims. Claims 1. A method for arranging planes in a printed circuit board, PCB, to which is attached a semiconductor device, the PCB having stacked metal layers extending from a top surface for receiving the semiconductor device to a bottom surface, the method comprising:

6 placing one or more core voltage supply planes in one or more metal layers of the stacked metal layers of the PCB, each core voltage supply plane of the one or more core voltage supply planes coupling a single core voltage supply to the semiconductor device, wherein: placing a primary core voltage supply plane of the one or more core voltage supply planes in a first predetermined metal layer of the stacked metal layers nearest to the semiconductor device; and placing others of the one or more core voltage supply planes below the primary core voltage supply plane in descending order based on the amount of supply noise the circuitry of the semiconductor device can accept that is driven by each of the one or more core voltage supply planes; and placing one or more input/output (I/O) voltage supply planes below the one or more core voltage supply planes in one or more metal layers of the stacked metal layers below the first predetermined metal layer, each I/O voltage supply plane of the one or more I/O voltage supply planes coupling a single I/O voltage supply to the semiconductor device, wherein: placing a lowest I/O voltage supply plane nearest to the one or more core voltage supply planes; and placing others of the one or more I/O voltage supply planes below the lowest I/O voltage supply plane in order of increasing voltage, wherein the primary core voltage supply plane comprises a primary core voltage supply that sources timing critical circuitry within the semiconductor device, and wherein the PCB comprises at least three stacked metal layers in which one or more core voltage supply planes and the one or more I/O voltage supply planes are placed. 2. The method of claim 1: 2 wherein placing the one or more core voltage supply planes comprises supplying power to and connecting to the clock circuitry of the semiconductor device; and wherein placing the one or more I/O voltage supply planes comprises supplying power to and connecting to I/O circuitry of the semiconductor device The method of claim 1, further comprising: assigning the third to last plane of the PCB to a highest voltage I/O voltage supply plane; and assigning the second to last plane of the PCB to a ground plane The method of claim 1, further comprising: placing a first ground plane proximate to a first side of each of the one or more core voltage supply planes and the one or more I/O voltage supply planes. 40. The method of claim 4, further comprising: placing a second ground plane proximate to a second side of each of the one or more core voltage supply planes and the one or more I/O voltage supply planes The method of claim 1, further comprising placing conductive lines to connect the one or more core voltage supply planes to a clock circuitry in the semiconductor device. 7. The method of claim 1, further comprising placing conductive lines to connect the one or more I/O voltage supply planes to an input/output circuitry of the semiconductor device A printed circuit board, PCB, to which is attached a semiconductor device, the PCB comprising an arrangement of planes and having stacked metal layers extending from a top surface for receiving the semiconductor device to a bottom surface, the PCB comprising: one or more core voltage supply planes in one or more metal layers of the stacked metal layers of the PCB, each core voltage supply plane of the one or more core voltage supply planes coupling a single core voltage supply to the semiconductor device, wherein: a primary core voltage supply plane of the one or more core voltage supply planes is placed in a first 6

7 predetermined metal layer of the stacked metal layers nearest to the semiconductor device; and others of the one or more core voltage supply planes are placed below the primary core voltage supply plane in descending order based on the amount of supply noise the circuitry of the semiconductor device can accept that is driven by each of the one or more core voltage supply planes; and one or more input/output (I/O) voltage supply planes placed below the one or more core voltage supply planes in one or more metal layers of the stacked metal layers below the first predetermined metal layer, each I/O voltage supply plane of the one or more I/O voltage supply planes coupling a single I/O voltage supply to the semiconductor device, wherein: a lowest I/O voltage supply plane is placed nearest to the one or more core voltage supply planes; and others of the one or more I/O voltage supply planes are placed below the lowest voltage I/O supply plane in order of increasing voltage wherein the primary core voltage supply plane comprises a primary core voltage supply that sources timing critical circuitry within the semiconductor device, and wherein the PCB comprises at least three stacked metal layers in which one or more core voltage supply planes and the one or more I/O voltage supply planes are placed. 9. The PCB of claim 8, wherein the one or more core voltage supply planes supply power to and are connected to the clock circuitry of the semiconductor device, while the one or more I/O voltage supply planes supply power to and are connected to I/O circuitry of the semiconductor device.. The PCB of claim 8, further comprising: 2 an assignment of the third to last plane of the PCB to a highest voltage I/O voltage supply plane; and an assignment of the second to last plane of the PCB to a ground plane. 11. The PCB of claim 8, further comprising: 30 a first ground plane placed proximate to a first side of each of the one or more core voltage supply planes and the one or more I/O voltage supply planes. 12. The PCB of claim 11, further comprising a second ground plane placed proximate to a second side of each of the one or more core voltage supply planes and the one or more I/O voltage supply planes The PCB of claim 8, further comprising conductive lines through which the one or more core voltage supply planes drive clock circuitry in the semiconductor device. 14. The PCB of claim 8, further comprising conductive lines through which the one or more I/O voltage supply planes drive input/output circuitry of the semiconductor device. 40 Patentansprüche 4 1. Verfahren zum Anordnen von Ebenen in einer Leiterplatte, PCB, die mit einem Halbleiterelement bestückt ist, wobei die Leiterplatte gestapelte Metallschichten aufweist, die sich von einer oberen Fläche für das Aufnehmen des Halbleiterelementes zu einer unteren Fläche erstrecken, wobei das Verfahren die folgenden Schritte aufweist: 0 Anordnen einer oder mehrerer Kernspannungsversorgungsebenen in einer oder mehreren Metallschichten der gestapelten Metallschichten der Leiterplatte, wobei eine jede Kernspannungsversorgungsebene der einen oder mehreren Kernspannungsversorgungsebenen eine einzelne Kernspannungsversorgung mit dem Halbleiterelement verbindet, wobei: eine primäre Kernspannungsversorgungsebene der einen oder mehreren Kernspannungsversorgungsebenen in einer ersten vorgegebenen Metallschicht der gestapelten Metallschichten angeordnet wird, die dem Halbleiterelement am nächsten ist; und andere der einen oder mehreren Kernspannungsversorgungsebenen unterhalb der primären Kernspannungsversorgungsebene in einer absteigenden Reihenfolge auf der Basis der Größe des Versorgungsrauschens angeordnet werden, das die Schaltung des Halbleiterelementes akzeptieren kann, das von einer jeden der einen oder mehreren Kernspannungsversorgungsebenen gesteuert wird; und 7

8 Anordnen einer oder mehrerer Eingangs/Ausgangs(I/O)spannungsversorgungsebenen unterhalb der einen oder mehreren Kernspannungsversorgungsebenen in einer oder mehreren Metallschichten der gestapelten Metallschichten unterhalb der ersten vorgegebenen Metallschicht, wobei eine jede Eingangs/Ausgangsspannungsversorgungsebene der einen oder mehreren Eingangs/Ausgangsspannungsversorgungsebenen eine einzelne Eingangs/Ausgangsspannungsversorgung mit dem Halbleiterelement verbindet, wobei: eine niedrigste Eingangs/Ausgangsspannungsversorgungsebene angeordnet wird, die der einen oder mehreren Kernspannungsversorgungsebenen am nächsten ist; und andere der einen oder mehreren Eingangs/Ausgangsspannungsversorgungsebenen unterhalb der niedrigsten Eingangs/Ausgangsspannungsversorgungsebene in der Reihenfolge der zunehmenden Spannung angeordnet werden, wobei die primäre Kernspannungsversorgungsebene eine primäre Kernspannungsversorgung aufweist, die die zeitkritische Schaltung innerhalb des Halbleiterelementes speist, und wobei die Leiterplatte mindestens drei gestapelte Metallschichten aufweist, in denen eine oder mehrere Kernspannungsversorgungsebenen und die eine oder mehreren Eingangs/Ausgangsspannungsversorgungsebenen angeordnet werden. 2. Verfahren nach Anspruch 1: bei dem das Anordnen der einen oder mehreren Kernspannungsversorgungsebenen das Zuführen von Strom zur und das Verbinden mit der Zeitgeberschaltung des Halbleiterelementes aufweist; und bei dem das Anordnen der einen oder mehreren Eingangs/Ausgangsspannungsversorgungsebenen das Zuführen von Strom zur und das Verbinden mit der Eingangs/Ausgangsschaltung des Halbleiterelementes aufweist Verfahren nach Anspruch 1, das außerdem die folgenden Schritte aufweist: 30 Zuordnen der dritten bis letzten Ebene der Leiterplatte zur Eingangs/Ausgangsspannungsversorgungsebene mit der höchsten Spannung; und Zuordnen der zweiten bis letzten Ebene der Leiterplatte zu einer Erdungsebene. 4. Verfahren nach Anspruch 1, das außerdem den folgenden Schritt aufweist: 3 Anordnen einer ersten Erdungsebene in unmittelbarer Nähe zu einer ersten Seite einer jeden der einen oder mehreren Kernspannungsversorgungsebenen und der einen oder mehreren Eingangs/Ausgangsspannungsversorgungsebenen.. Verfahren nach Anspruch 4, das außerdem den folgenden Schritt aufweist: 40 Anordnen einer zweiten Erdungsebene in unmittelbarer Nähe zu einer zweiten Seite einer jeden der einen oder mehreren Kernspannungsversorgungsebenen und der einen oder mehreren Eingangs/Ausgangsspannungsversorgungsebenen Verfahren nach Anspruch 1, das außerdem den Schritt des Anordnens von leitfähigen Leitungen aufweist, um die eine oder mehreren Kernspannungsversorgungsebenen mit einer Zeitgeberschaltung im Halbleiterelement zu verbinden Verfahren nach Anspruch 1, das außerdem den Schritt des Anordnens von leitfähigen Leitungen aufweist, um die eine oder mehreren Eingangs/Ausgangsspannungsversorgungsebenen mit einer Eingangs/Ausgangsschaltung des Halbleiterelementes zu verbinden. 8. Leiterplatte, PCB, die mit einem Halbleiterelement bestückt ist, wobei die Leiterplatte eine Anordnung von Ebenen und gestapelte Metallschichten aufweist, die sich von einer oberen Fläche für das Aufnehmen des Halbleiterelementes zu einer unteren Fläche erstrecken, wobei die Leiterplatte aufweist: eine oder mehrere Kernspannungsversorgungsebenen in einer oder mehreren Metallschichten der gestapelten Metallschichten der Leiterplatte, wobei eine jede Kernspannungsversorgungsebene der einen oder mehreren Kernspannungsversorgungsebenen eine einzelne Kernspannungsversorgung mit dem Halbleiterelement verbindet, wobei: 8

9 eine primäre Kernspannungsversorgungsebene der einen oder mehreren Kernspannungsversorgungsebenen in einer ersten vorgegebenen Metallschicht der gestapelten Metallschichten angeordnet wird, die dem Halbleiterelement am nächsten ist; und andere der einen oder mehreren Kernspannungsversorgungsebenen unterhalb der primären Kernspannungsversorgungsebene in einer absteigenden Reihenfolge auf der Basis der Größe des Versorgungsrauschens angeordnet werden, das die Schaltung des Halbleiterelementes akzeptieren kann, das von einer jeden der einen oder mehreren Kernspannungsversorgungsebenen gesteuert wird; und eine oder mehrere Eingangs/Ausgangs(I/O)spannungsversorgungsebenen unterhalb der einen oder mehreren Kernspannungsversorgungsebenen in einer oder mehreren Metallschichten der gestapelten Metallschichten unterhalb der ersten vorgegebenen Metallschicht angeordnet werden, wobei eine jede Eingangs/ Ausgangsspannungsversorgungsebene der einen oder mehreren Eingangs/Ausgangsspannungsversorgungsebenen eine einzelne Eingangs/Ausgangsspannungsversorgung mit dem Halbleiterelement verbindet, wobei: 2 30 eine niedrigste Eingangs/Ausgangsspannungsversorgungsebene angeordnet wird, die der einen oder mehreren Kernspannungsversorgungsebenen am nächsten ist; und andere der einen oder mehreren Eingangs/Ausgangsspannungsversorgungsebenen unterhalb der niedrigsten Eingangs/Ausgangsspannungsversorgungsebene in der Reihenfolge der zunehmenden Spannung angeordnet werden, wobei die primäre Kernspannungsversorgungsebene eine primäre Kernspannungsversorgung aufweist, die die zeitkritische Schaltung innerhalb des Halbleiterelementes speist, und wobei die Leiterplatte mindestens drei gestapelte Metallschichten aufweist, in denen eine oder mehrere Kernspannungsversorgungsebenen und die eine oder mehreren Eingangs/Ausgangsspannungsversorgungsebenen angeordnet werden. 9. Leiterplatte nach Anspruch 8, bei der die eine oder mehreren Kernspannungsversorgungsebenen Strom zur Zeitgeberschaltung des Halbleiterelementes zuführen und damit verbunden sind, während die eine oder mehreren Eingangs/Ausgangsspannungsversorgungsebenen Strom zur Eingangs/Ausgangsschaltung des Halbleiterelementes zuführen und damit verbunden sind.. Leiterplatte nach Anspruch 8, die außerdem aufweist: 3 eine Zuordnung der dritten bis letzten Ebene der Leiterplatte zur Eingangs/Ausgangsspannungsversorgungsebene mit der höchsten Spannung; und eine Zuordnung der zweiten bis letzten Ebene der Leiterplatte zu einer Erdungsebene. 11. Leiterplatte nach Anspruch 8, die außerdem aufweist: 40 eine erste Erdungsebene, die in unmittelbarer Nähe zu einer ersten Seite einer jeden der einen oder mehreren Kernspannungsversorgungsebenen und der einen oder mehreren Eingangs/Ausgangsspannungsversorgungsebenen angeordnet ist Leiterplatte nach Anspruch 11, die außerdem eine zweite Erdungsebene aufweist, die in unmittelbarer Nähe zu einer zweiten Seite einer jeden der einen oder mehreren Kernspannungsversorgungsebenen und der einen oder mehreren Eingangs/Ausgangsspannungsversorgungsebenen angeordnet ist. 13. Leiterplatte nach Anspruch 8, die außerdem leitfähige Leitungen aufweist, mittels der die eine oder mehreren Kernspannungsversorgungsebenen die Zeitgeberschaltung im Halbleiterelement steuern Leiterplatte nach Anspruch 8, die außerdem leitfähige Leitungen aufweist, mittels der die eine oder mehreren Eingangs/Ausgangsspannungsversorgungsebenen die Eingangs/Ausgangsschaltung des Halbleiterelementes steuern. Revendications 1. Procédé d agencement de plans dans une carte de circuit imprimé, PCB, sur laquelle est fixé un dispositif semiconducteur, la PCB comportant des couches métalliques empilées s étendant d une surface supérieure, pour recevoir le dispositif semi-conducteur, vers une surface inférieure, le procédé comprenant les étapes ci-dessous : 9

10 2 placement d un ou de plusieurs plans d alimentation en tension de base dans une ou plusieurs couches métalliques des couches métalliques empilées de la PCB, chaque plan d alimentation en tension de base du ou des plusieurs plans d alimentation en tension de base couplant une seule alimentation en tension de base au dispositif semi-conducteur ; placement d un plan d alimentation en tension de base primaire du ou des plusieurs plans d alimentation en tension de base dans une première couche métallique prédéterminée des couches métalliques empilées, la plus proche du dispositif semi-conducteur ; et placement d autres plans du ou des plusieurs plans d alimentation en tension de base au-dessous du plan d alimentation en tension de base primaire, dans un ordre descendant, sur la base de l importance du bruit d alimentation que peut accepter le dispositif semi-conducteur entraîné par chacun du ou des plusieurs plans d alimentation en tension de base; et placement d un ou de plusieurs plans d alimentation en tension d entrée/de sortie (I/O) au-dessous du ou des plusieurs plans d alimentation en tension de base dans une ou plusieurs couches métalliques des couches métalliques empilées au-dessous de la première couche métallique prédéterminée, chaque plan d alimentation en tension d entrée/sortie du ou des plusieurs plans d alimentation en tension d entrée/sortie couplant une seule alimentation en tension d entrée/sortie au dispositif semi-conducteur ; placement d un plan d alimentation en tension d entrée/sortie minimale le plus près du ou des plusieurs plans d alimentation en tension de base ; et placement d autres plans du ou des plusieurs plans d alimentation en tension d entrée/sortie au-dessous du plan d alimentation en tension d entrée/sortie minimale, dans l ordre de l accroissement de la tension ; le plan d alimentation en tension de base primaire comprenant une alimentation en tension de base primaire approvisionnant un circuit de synchronisation critique dans le dispositif semi-conducteur, la PCB comprenant au moins trois couches métalliques empilées, dans lesquelles sont placées un ou plusieurs plans d alimentation en tension de base et le ou les plusieurs plans d alimentation en tension d entrée/de sortie. 2. Procédé selon la revendication 1, dans lequel : 30 l étape de placement du ou des plusieurs plans d alimentation en tension de base comprend l alimentation en énergie du circuit d horloge du dispositif semi-conducteur et la connexion à celui-ci; et l étape de placement du ou des plusieurs plans d alimentation en tension d entrée/de sortie comprend l alimentation en énergie du circuit d entrée/de sortie du dispositif semi-conducteur et la connexion à celui-ci. 3. Procédé selon la revendication 1, comprenant en outre les étapes ci-dessous : 3 affectation des troisième au dernier plans de la PCB au plan d alimentation en tension d entrée/sortie maximale ; et affectation des deuxième à dernier plans de la PCB à un plan de masse Procédé selon la revendication 1, comprenant en outre l étape ci-dessous : placement d un premier plan de masse près d un premier côté de chacun du ou des plusieurs plans d alimentation en tension de base et du ou des plusieurs plans d alimentation en tension d entrée/de sortie. 4. Procédé selon la revendication 4, comprenant en outre l étape ci-dessous : placement d un deuxième plan de masse près d un deuxième côté de chacun du ou des plusieurs plans d alimentation en tension de base et du ou des plusieurs plans d alimentation en tension d entrée/de sortie Procédé selon la revendication 1, comprenant en outre l étape de mise en place de lignes conductrices pour connecter le ou les plusieurs plans d alimentation en tension de base à un circuit d horloge dans le dispositif semi-conducteur. 7. Procédé selon la revendication 1, comprenant en outre l étape de mise en place de lignes conductrices pour connecter le ou les plusieurs plans d alimentation en tension d entrée/de sortie à un circuit d entrée/de sortie du dispositif semiconducteur. 8. Carte de circuit imprimé, PCB, sur laquelle est fixé un dispositif semi-conducteur, la PCB comprenant un agencement de plans et comportant des couches métalliques empilées s étendant d une surface supérieure, pour recevoir le dispositif semi-conducteur, vers une surface inférieure, la PCB comprenant :

11 un ou plusieurs plans d alimentation en tension de base dans une ou plusieurs couches métalliques des couches métalliques empilées de la PCB, chaque plan d alimentation en tension de base du ou des plusieurs plans d alimentation en tension de base couplant une seule alimentation en tension de base au dispositif semiconducteur ; dans laquelle : un plan d alimentation en tension de base primaire du ou des plusieurs plans d alimentation en tension de base est placé dans une première couche métallique prédéterminée des couches métalliques empilées, la plus proche du dispositif semi-conducteur ; et d autres plans du ou des plusieurs plans d alimentation en tension de base sont placés au-dessous du plan d alimentation en tension de base primaire, dans un ordre descendant, sur la base de l importance du bruit d alimentation pouvant être acceptée par le dispositif semi-conducteur, entraîné par chacun du ou des plusieurs plans d alimentation en tension de base ; et un ou plusieurs plans d alimentation en tension d entrée/de sortie (I/O) sont placés au-dessous du ou des plusieurs plans d alimentation en tension de base dans une ou plusieurs couches métalliques des couches métalliques empilées, au-dessous de la première couche métallique prédéterminée, chaque plan d alimentation en tension d entrée/de sortie du ou des plusieurs plans d alimentation en tension d entrée/de sortie couplant une seule alimentation en tension d entrée/de sortie au dispositif semi-conducteur ; dans laquelle : 2 un plan d alimentation en tension d entrée/de sortie minimale est placé le plus près du ou des plusieurs plans d alimentation en tension de base ; et d autres plans du ou des plusieurs plans d alimentation en tension d entrée/de sortie sont placés au-dessous du plan d alimentation en tension d entrée/de sortie minimale, dans l ordre de l accroissement de la tension ; le plan d alimentation en tension de base primaire comprend une alimentation en tension de base primaire approvisionnant un circuit de synchronisation critique dans le dispositif semi-conducteur, la PCB comprenant au moins trois couches métalliques empilées, dans lesquelles sont placés le ou les plusieurs plans d alimentation en tension de base et le ou les plusieurs plans d alimentation en tension d entrée/de sortie PCB selon la revendication 8, dans laquelle le ou les plusieurs plans d alimentation en tension de base alimentent le circuit d horloge du dispositif semi-conducteur et sont connectés à celui-ci, le ou les plusieurs plans d alimentation en tension d entrée/de sortie alimentant le circuit d entrée/de sortie du dispositif semi-conducteur et étant connectés à celui-ci.. PCB selon la revendication 8, comprenant en outre : 3 une affectation des troisième à dernier plans de la PCB à un plan d alimentation en tension d entrée/de sortie maximale ; et une affectation des deuxième à dernier plans de la PCB à un plan de masse. 11. PCB selon la revendication 8, comprenant en outre : 40 un premier plan de masse placé près d un premier côté de chacun du ou des plusieurs plans d alimentation en tension de base et du ou des plusieurs plans d alimentation en tension d entrée/de sortie PCB selon la revendication 11, comprenant en outre un deuxième plan de masse placé près d un deuxième côté de chacun du ou des plusieurs plans d alimentation en tension de base et du ou des plusieurs plans d alimentation en tension d entrée/de sortie. 13. PCB selon la revendication 8, comprenant en outre des lignes conductrices, à travers lesquelles le ou les plusieurs plans d alimentation en tension de base entraînent le circuit d horloge dans le dispositif semi-conducteur PCB selon la revendication 8, comprenant en outre des lignes conductrices, à travers lesquelles le ou les plusieurs plans d alimentation en tension d entrée/de sortie entraînent le circuit d entrée/de sortie du dispositif semi-conducteur. 11

12 12

13 13

14 14

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16 16

17 17

18 18

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20

21 REFERENCES CITED IN THE DESCRIPTION This list of references cited by the applicant is for the reader s convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard. Patent documents cited in the description US B [00] US 0229 A [0011] 21

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