MROD-X performance tests H. Boterenbrood, J. Vermeulen

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1 MRO-X performance tests H. Boterenbrood, J. Vermeulen ounter measures maximum trigger rate rigger vi out IM MRO RIN RG MRO MRO MRO Loopback fibers rigger vi: only used for random triggers Busy Busy and rigger via backplane IM: can generate fixed rate (non-random) trigger, OR of busy signals suppresses Internal or external trigger. rigger signals sent to MROs fire internal data generators. MRO PRR 2 Nov / JV 1

rigger vi: only used for random triggers Busy Busy and rigger via backplane IM: can generate fixed rate

2 ata flow into, inside and out of MRO-X MRO-In MRO-In MRO-In MRO-In MRO-In MRO-Out ROL MRO-In MRO-In MRO-In : 160 or 100 MByte/s : 160 MByte/s ROL: 160 or 200 MByte/s MRO PRR 2 Nov / JV 2

3 MRO PRR 2 Nov / JV 3 ata on the link I L E I L E 17 I L E I L E S E P A R A O R S E P A R A O R est generator in MRO-X: inserts ever 32 cycles 2 idle cycles: effective bandwidth = 32 / 34 = 94.12% of nominal bandwidth, taking into account the separator word results in * 18 / 19 = 89.16% With 40 ns per word the effective bandwidth is: MByte/s With 25 ns per word the effective bandwidth is: MByte/s SM: 2 idles after 19 words: effective bandwidth = 19 / 21 = 90.48% of nominal bandwidth, taking into account the separator word results in * 18 / 19 = 85.71% With 40 ns per word the effective bandwidth is: MByte/s With 25 ns per word the effective bandwidth is: MByte/s

32 cycles 2 idle cycles: effective bandwidth = 32 / 34 = 94.12% of nominal bandwidth, taking into account the separator word results in 94.12 * 18 / 19 = 89.

4 Results with test generator in MRO-X 18 s for each input limits rate to 89.1 MByte/s 1 input 2 inputs 3 inputs 4 inputs 6 inputs 8 inputs 2-8 inputs or 1 input with < 8 words / : maximum rate not determined by link MRO PRR 2 Nov / JV 4

5 ata added to data MRO-In MRO-In MRO-In MRO-In MRO-In MRO-In MRO-In MRO-In MRO-In: strips separator words, MRO-Out adds one "magic" word (for MRO-1 compatibility) per event adds 4 additional words per event. via the link idles and two more words are sent per event, but as these links are not fully utilized these data never affect the maximum event rate. : 160 or 100 MByte/s :160 MByte/s ROL: 160 or 200 MByte/s MRO-Out, for each event: strips "magic" words adds 9 header and 4 trailer words adds BOB and EOB words adds BOF and EOF control words i.e. in total 17 words per event added, up to 8 words removed MRO PRR 2 Nov / JV 5 ROL

via the link idles and two more words are sent per event, but as these links are not fully utilized these data never affect the maximum event rate.

6 Inverse rate for 1 and 2 inputs 18 s for each input 100 khz corresponds to MByte/s = bandwidth ROL 2 inputs 1 input 1 input / 2 inputs FPGA MRO-In determines maximum rate 1 input corresponds to MByte/s = bandwidth link NB: time per event = 1 / rate measured MRO PRR 2 Nov / JV 6

2 MByte/s = bandwidth ROL 2 inputs 1 input 1 input / 2 inputs FPGA MRO-In

7 1 input: data rate below maximum (89.1 MByte/s) for few words per 89 MByte / s IM trigger and Busy seem to interlock in linear part: f 2 words = 600 khz (max. freq. IM), f 3 words = 412 khz, f 5 words = 247 khz, i.e. f ~ 1 / of words (NB: 0.6 x 412 = 247) 5 words / 3 words / 2 words / Behavior for larger number of s determined by MRO-In FPGA MRO PRR 2 Nov / JV 7

part: f 2 words = 600 khz (max. freq. IM), f 3 words = 412 khz, f 5 words = 247 khz, i.e. f ~ 1 / of words (NB: 0.

8 Inverse rate for single input for few words per Per additional extra: for 2 words per : s, for 3 words per : s, for 5 words per : s. -> for each word: s (FPGA clock of 40 MHz) -> + per s, i.e. 5 clock cycles MRO PRR 2 Nov / JV 8

200 s, for 5 words per : 0.250 s. -> for each word: 0.

9 Inverse rate for single input for few words per Plot of previous slide Per event: s, i.e. 25 clock cycles -> 1 cycle per (active or inactive) 18 cycles -> transfer of "magic word" + additional words into the output FIFO 5 cycles -> overhead 2 cycles + 25 cycles MRO PRR 2 Nov / JV 9

inactive) 18 cycles -> transfer of "magic word" + additional words into

10 Inverse rate for 1 or 2 inputs for few words per 18 s for each input 2 inputs 100 khz 1 input 1 input 1 input / 2 inputs FPGA MRO-In determines maximum rate Plot of slide 6 ransfer of 1 additional word for 18 s -> 18 cycles, i.e s. For 18 s active: per cycles 108 cycles per event 7 cycles + total:115 cycles, i.e s MRO PRR 2 Nov / JV 10

ransfer of 1 additional word for 18 s -> 18 cycles, i.e. 0.45 s.

With zero-suppression on: inverse rate for single input, 18 s active 3 time stamp words 1 time stamp word Per additional time stamp word 0.025 s, i.e. 1 clock cycle is needed Without time stamps ~3.

11 With zero-suppression on: inverse rate for single input, 18 s active 3 time stamp words 1 time stamp word Per additional time stamp word s, i.e. 1 clock cycle is needed Without time stamps ~3.775 s is needed, this comes from: 7 cycles overhead per event (2 + 5 for outputting data words) = s 6 cycles per (1 + 5 per active partition) = 108 cycles = s 2 cycles per for reading BO/EO words = 36 cycles = s s MRO PRR 2 Nov / JV 11

775 s is needed, this comes from: 7 cycles overhead per event (2 + 5 for outputting data words) = 0.

12 ROL bandwidth determines throughput in most cases 18 s for each input MRO-In FPGA determines throughput ROL determines throughput link determines throughput BOB and EOB control words not taken into account in bandwidth calculation MRO PRR 2 Nov / JV 12

throughput link determines throughput BOB and EOB control words

13 ROL bandwidth determines throughput for event rates < 100 khz 18 s for each input Rate limited by MRO-In FPGA 100 khz Rate limited by link Rate limited by ROL MRO PRR 2 Nov / JV 13

14 Increment in inverse rate for > 2 inputs consistent with ROL speed 18 s for each input 8 inputs 6 inputs 4 inputs 3 inputs 2 inputs / (8 x 18) = s / (6 x 18) = s / (4 x 18) = s / (3 x 18) = s / (2 x 18) = s As expected for ROL of 160 MByte/s (0.025 s per 32-bit word) MRO PRR 2 Nov / JV 14

7005 / (6 x 18) = 0.025 s 1.7996 / (4 x 18) = 0.025 s 1.345 / (3 x 18) = 0.025 s 0.

15 Offset in time per event as function of the numbers of inputs Per input: ~0.15 s for 4 words to be transferred via ROL -> + 2 cycles per active link Per event: ~0.875 s = 35 cycles for 17 words to be transferred = 17 cycles 18 cycles additional overhead: 2 per link -> 16 cycles + 2 per event MRO PRR 2 Nov / JV 15

16 Rate limitation by MRO-In FPGA 18 s active limit due to clock of 40 MHz 50 MHz FPGA clock 200 Mbyte/s) 40 MHz FPGA clock limit due to clock of 25 MHz Bandwidth 100 khz 12 words per, with > 1 input link throughput limited by bandwidth 25 MHz, 40 MHz : limits MHz, 40 MHz : FPGA limits 100 khz MRO PRR 2 Nov / 40 MHz, 50 MHz : limits 100 khz 16

throughput limited by bandwidth ROL @ 25 MHz, FPGA @ 40 MHz : limits throughput @ 100 khz @ 40 MHz, FPGA @ 40

17 Rate limitation by MRO-Out FPGA / ROL for 40 and 50 MHz clock, 18 s for 6 or 8 inputs inputs / 40 MHz inputs / 50 MHz 6 inputs / 40 MHz 6 inputs / 50 MHz MRO-Out FPGA clock 40 -> 50 MHz: throughput increases by ~1.3 for 6 inputs (at 100 khz and for 6 * 18 s all outputting 3-4 words, note that 4 words correspond to header, time stamp for leading edge, time stamp for trailing edge and trailer) MRO PRR 2 Nov / JV 17

9 8 inputs / 50 MHz 6 inputs / 40 MHz 6 inputs / 50 MHz MRO-Out FPGA clock 40 -> 50 MHz: throughput increases

The new frontier of the DATA acquisition using 1 and 10 Gb/s Ethernet links. Filippo Costa on behalf of the ALICE DAQ group

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