1 Intel Itanium Architecture Roadmap and Technology Update Dr. Gernot Hoyler Technical Marketing EMEA
2 Intel Itanium Architecture Growth MARKET Over 3x revenue growth Y/Y* More than 10x growth* in shipments of large SMP systems (64+) IDC Worldwide Quarterly Server Tracker, August 2004 SOFTWARE Over 100% Y/Y growth 2,000 HARDWARE # OEM server models keep growing P, 4P P - 128P of 9 RISC vendors selling Intel Itanium-based servers END-CUSTOMERS 38 of Global 100 companies using Intel Itanium-based servers today 1, forecast of 2000 applications reached TODAY! 0 1H 03 2H 03 1H 04 2H 04 High profile wins: General Mills, Pfizer, Thomson Financial, Procter and Gamble, The Weather Channel, First American Title, Motorola Other names and brands may be claimed as the property of others.
3 Broad Ecosystem Support Application Choice Operating System Choice System Vendor & Platform Choice OpenVMS* >2000 native applications 32-bit application support with IA-32 Execution Layer Windows*, Linux*, and Unix* support >70 vendors selling today 20 large SMP systems 2-way to 256-way systems 8 of 9 RISC vendors support Broad industry support Choice that you don t t get with RISC
4 Itanium Processor Family: A Strategic Product for Intel Design teams working on more than 6 future processors
5 Intel Itanium Processor Family future Itanium 2 Madison** Madison9M Montecito ** Tukwila** Common Platform 800MHz 4MB L3-Cache 460GX Chip-set OEM Chip-sets 180nm 1GHz 3MB il3-cache E8870 Chip-set OEM Chip-sets 180nm 1.5GHz 6MB il3-cache E8870 Chip-set OEM Chip-sets 130nm 1.6GHz 9MB il3-cache E8870 Chip-set OEM Chip-sets 130nm >>1.6GHz 24MB il3- Cache Dual-Core E8870 OEM Chip-sets 90nm All features and dates specified are targets provided for planning purposes only and are subject to change. Multi-Core Developed by former Alpha team **codename
6 Common Platform & Infrastructure Today: Itanium Processor exceeds RISC performance & price / perf Today: Itanium platform delivering superior price / performance vs Intel Xeon Processor on transaction processing 30% more transactions at 10% incremental cost of hardware platform/ OS / database*** 07: Itanium platform cost reduced to parity with Intel Xeon processor- based platforms Common platform components to lead to common platform infrastructure over time All features and dates specified are targets provided for planning purposes only and are subject to change without notice.
7 Current Architecture or Solutions Choice and Flexibility for Evolving Enterprise Servers Transition Benefits Architecture of Choice RISC Architecture Target Applications Database, ERP, BI, HPC Exceptional performance choice of operating systems, software and hardware vendors TODAY Mission critical 64-bit architecture Premier performance, reliability, scalability; cost effective vs. RISC 64-bit support via Intel EM64T, IA-32 Architecture great performance for 32-bit applications Target Applications MP: SCM, CRM, BI, ERP DP: HPC, Application Server, Workgroup E-Commerce, E Portals, Firewall/Security, Workstation apps Mainstream 64-bit architecture; price performance reliability * Performance tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance.
8 Future technologies: Processor and Platform Enhancements Multiple Cores and Thread Virtualization Power Management
9 Intel Processor Technology Trends Era of Thread & Core Parallelism Era of Instruction Parallelism All features and dates specified are targets provided for planning purposes only and are subject to change without notice
10 Enterprise Multi-Core Transition dual core a natural evolution 4 or more cores + cache TODAY Single Core Dual Core Future Multi-Core 2 or more cores + cache All products, dates and features are preliminary and subject to change without notice
11 Itanium Architecture Optimized for Multi-Core Architecture: Parallelism and many registers to keep data on-chip Core size: Smaller than IA-32, up to 2x more cores per die on than on IA-32 All products, dates, and figures are preliminary and are subject to change without notice. * EPIC is Itanium s architecture Explicitly Parallel Instruction Set Computing All features and dates specified are targets provided for planning purposes only and are subject to change without notice.
12 Multi-Threading Approaches Sharing resources High utilization High complexity Medium latency hiding Medium utilization Low complexity Medium latency hiding Temporal A A A B B B B B A A A A B B B A A A B B B B B Single thread/cycle Event A A A A A A A A A B B B B B B B B B B B B Multiple thread/cycle A A A B B A A B B B A A B B B A A A B B B A A B B B B Medium utilization Low complexity High latency hiding Event for the core and Multiple for the caches
13 Montecito Multi-Threading Serial Execution A i Idle A i+1 B i Idle B i+1 Montecito Multi-threaded threaded Execution A i Idle A i+1 B i B i+1 Multi-threading threading decreases stalls and increases performance
14 Optimal Dynamic Thread Switching Determine when execution is stalled for long latency operations Practical Predict that a long latency event will stall execution Hysteresis to avoid needless switches gives software control Effective solution allowing streaming and access clumping
15 Multi-Level Parallelism MULTI-CORE DUAL-CORE MULTI-THREADING THREADING SINGLE CORE (ILP, SIMD) ILP,SIMD Thread Core Die/Socket All features and dates specified are targets provided for planning purposes only and are subject to change without notice
16 Performance Innovations Itanium Processor Performance Strategy: Increased performance/thread, then increased number of threads Source: Intel Corporation All data measured at Intel on current processors. Projections on future processors based on Intel estimates using similar workload testing at Intel (Transaction processing using 64GB of memory, Floating point using 4GB). Increased Performance/Thread Floating Point Performance (Single thread) - Relative Performance Driven by: Increased frequency Increased L3 cache Increased bus speed Itanium 2 Processor Itanium 2 6M Itanium 2 9M Montecito Multi-threaded threaded Performance Montecito: 4 virtual processors 4S Transaction Processing Relative Performance Itanium 2 Processor Itanium 2 6M Itanium 2 9M Montecito Driven by: Dual core Montecito Multi-threading threading support in Montecito *Third-party marks and brands are the property of their respective owners; Performance tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance. Buyers should consult other sources of information to evaluate the performance of systems or components they are considering purchasing. All products, dates, and figures are preliminary and are subject to change without any notice. Copyright Intel Corporation 2004.
17 First Implementation of Key Features: Montecito Core Montecito Core Core 1 Core 2 Key Processor Features Intel s s first dual-core processor Intel s s first processor with >1 billion transistors 24 MB L3 cache Multi-threading threading Compatible with existing Dualcore Itanium 2-based 2 systems Pellston, Foxton and Silvervale Technology Targeting H Billion Transistors 1MB L2I 2 Way Multi-threading threading 2x12MB L3 caches with Pellston L3 Cache System Bus Arbiter L3 Cache Multiple cores, Multiple threads and L3 Cache on ONE die 90nm Power Management/ Frequency Boost (Foxton)
18 Montecito Technologies Pellston Technology Automatically disables cache lines in the event of a hard cache memory error Allows processor and system to continue normal operation Improve reliability / / uptime uptime Silvervale Technology VM1 VM-n Foxton Technology Processor boosts performance dynamically based on application power consumption (up to 10% freq.) Largest performance impact expected on transaction processing More More performance / / no no platform modifications App MRTE OS(1) Memory Network App Virtual Machine Monitor Silvervale Technology Shared Physical Host Hardware Processors Storage App MRTE OS(N) App Graphics Keyboard / Mouse HW Value Provides the hooks for a hardware supported virtualisation Enables the Virtual Machine Monitor to be more robust and shows a higher performance Next Next level level of of Server Server Consolidation Performance tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance. Buyers should consult other sources of information to evaluate the performance of systems or components they are considering purchasing. All products, dates, and figures are preliminary and are subject to change without any notice. Copyright Intel
19 Designing for Power Leakage current increases exponentially as process size decreases linearly Business as usual is not an option 45nm CPU might need 1kW
20 Transistor Design Roadmap Extending Moore s Law: Continued World Leading Transistor Scaling and Novel Structures for Low Power / High Performance All features and dates specified are targets provided for planning purposes only and are subject to change without notice
21 Power Reduction Features In addition to on-going improvements such as voltage scaling, new power reduction features are planned for each process generation Strained silicon Sleep transistors 90nm 65nm 45nm 32nm High-k/ metal gate Tri-gate transistors All features and dates specified are targets provided for planning purposes only and are subject to change without notice
22 Power Management Innovation Growing Capabilities over TIME Reduced Power via Management Demand Based Switching (DBS( DBS) Aggressive use of C1E state Power Prediction/Monitoring Report Configuration Power (PConfig) Monitor Power (PSMI( PSMI) SILICON TRANSISTORS PACKAGES HEAT SINKS SYSTEMS FACILITIES Lower power cores Process (65nm( 65nm) Proliferate Benefits
23 Advances in Memory Technology DDR2 Features DRAM Technology for Multiple Generations Higher Bandwidth Lower Power On Die Termination Four DIMMs per Channel IT Benefits Increased Platform Longevity Higher System Performance Increased Server Density Increased Memory Density Lower cost memory configurations Note: Comparison relative to DDR333
27 PCI Express* for I/O Advantages Performance Performance Bottleneck Processor Network I/O Source: Merrill Lynch IDC expects PCI Express to be a leading contender in keeping the future IT infrastructure fed with lots of I/O delivered quickly and managed securely. - IDC, Vernon Turner, June 2003 I/O Breakthrough Keep pace with rest of platform Lower Cost Standards-based & Serial I/O drive inherently lower product development & manufacturing, and TCO Investment Protection Future proofing through 10 year roadmap. Increased RAS. Rapid Enterprise Adoption Majority of OEMs/ODMs with PCIe slots, compelling 04 adapter availability, and strong IHV development plans
28 PCI Express* Performance Mellanox Technologies Data Mellanox Measurements: Realizing over 2.9x the bandwidth of PCI-X X % reduction in latency reduced CPU overhead Additional performance possible with tuning MB/s InfiniHost III Ex Bandwidth (Actual) IB Over PCI-X Uni-directional B/W IB Single Port Over 8x PCI Express IB Dual Port over 8x PCI Express Bi-directional B/W **Source: Mellanox Technologies(March 04) Full report available at : PCI-Express delivers significant performance improvement over PCI-X
29 Vielen Dank!
31 Long Term Goal: 1M Transactions per Minute Today In 2007 With planned performance improvements, a 4-way 4 Itanium -based server in 07 could deliver equivalent OLTP of a current 64-way system, delivering dramatically Lower TCO Lower power consumption Higher density Shown are representations of 64-way system (today) and 4-way system (2007). Not to scale. All products, dates, comparisons, and information are preliminary and subject to change without notice.
33 IA-32 Execution Layer Availability IPF Code Itanium 2 processor IA-32 Code IA-32 EL IA-32 H/W Historically, support of IA-32 applications has been carried out by on-die hardware When using OS with IA-32 EL, support for IA-32 applications is provided by IA-32 EL Operating System Gives access to the ia-32 EcoSystem Microsoft* Windows* Server 2003 Enterprise Edition Microsoft Windows Server 2003 Datacenter Edition Microsoft Windows XP Professional 64-Bit Edition Red Hat* Enterprise Linux 3 SGI* Advanced Linux Environment with ProPack* 3.0 SUSE* Linux Entreprise Server 9 Asianux* Red Flag* Advanced Server Red Flag DC Server Miracle Linux* Available 2H 04 2H 04 2H 04 2H 04 For Microsoft Windows, IA-32 EL is currently available at Microsoft Download Center,, and will ship with Windows Server 2003 SP1 RTM For Linux, IA-32 EL ships or will ship with the OS, as indicated by the availability date 1 Asianux 1.0 includes Red Flag Advanced Server 4.1 and Miracle Linux 3.0. Performance Scaling with Future Processors 1 SPECint_base2000* Itanium 2 Itanium Processor Processor 1.5 GHz Family IA-32 EL All products, dates, comparisons and information are preliminary and subject to change without notice. ~ Xeon Processor MP 1.5 GHz '03 '04 '05 '06
34 SW Tools, Cross Platform Support Currently available Planned Single Source Code Multiple Platforms Itanium 2, 2, Xeon (EM64T/32Bit) and and XScale Processor
35 Foxton Technology Dynamically adjust Voltage (V) & frequency (f) Exploit full power envelope for all applications Demand Based Switching and flexible power settings Large power change small frequency change (P=fCV 2 ) 3% power change with only 1% frequency change Monitor/calculate power and temperature Set Voltage to the minimum value needed to support highest frequency Over power and/or temperature results in voltage change Frequency responds to global and local voltage
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