Scheduling Semiconductor Manufacturing Operations: Problems, Solution Techniques, and Future Challenges

Transcription

1 MISTA 2009 Scheduling Semiconductor Manufacturing Operations: Problems, Solution Techniques, and Future Challenges Lars Mönch John W. Fowler Stéphane Dauzère-Pérès Scott J. Mason Oliver Rose Abstract In this paper, we discuss scheduling problems in semiconductor manufacturing. Starting from describing the manufacturing process, we identify typical scheduling problems that can be found in semiconductor manufacturing systems. We describe batch scheduling problems, ob shop scheduling problems, scheduling problems with secondary resources, multiple orders per ob scheduling problems, and scheduling problems related to cluster tools. We also present important solution techniques that are used to solve these scheduling problems by means of specific examples, and report on known implementations. Finally, we summarize some challenges in scheduling semiconductor manufacturing operations. 1 Introduction Recently, the electronics industry has become the largest industry in the world. A key aspect of this industry is the manufacturing of integrated circuits. In semiconductor manufacturing, integrated circuits are produced on silicon wafers. In the past, efforts for reducing costs included decreasing the size of the chips, increasing the wafer sizes, and improving the yield, while simultaneously trying to improve operational processes inside the semiconductor manufacturing systems. Currently, it seems that the improvement of operational processes creates the best opportunity to realize the necessary cost reductions. Semiconductor manufacturing is very capital intensive. Lots (denoted as obs throughout the rest of this paper to conform with the scheduling literature) are the moving entities in semiconductor manufacturing systems. Each ob contains a fixed number of wafers. The process conditions are very complex. We have to deal with parallel machines (also referred to as tools), different types of processes (batch and serial), sequence-dependent setup times, prescribed customer due dates for the obs, and re-entrant process flows. Very often, we also have to cope with a large number of different products and a product mix that changes over time. Semiconductor manufacturing systems are prototypical examples for complex ob shops. Lars Mönch University of Hagen Lars.Moench@fernuni-hagen.de John W. Fowler Arizona State University, Tempe John.Fowler@asu.edu Stéphane Dauzère-Pérès Ecole des Mines de Saint-Etienne Dauzere-Peres@emse.fr Scott J. Mason University of Arkansas, Fayetteville mason@uark.edu Oliver Rose Dresden University of Technology oliver.rose@tu-dresden.de 192

2 Crucial factors of competitiveness in semiconductor manufacturing are the ability to rapidly incorporate advanced technologies in electronic products, ongoing improvement of manufacturing processes, and, last but not least, the capability of meeting due dates for optimal customer satisfaction. In a situation where prices as well as the state of technology have settled at a certain level, the capability of meeting due dates along with the reduction of cycle time probably has become the most decisive factor to stand the fierce competition in the global market place. Cycle time is defined in this context as the time a ob of wafers needs to travel through the semiconductor wafer manufacturing process including queue time, processing time, and transit time. Consequently, operations managers are under increasing pressure to ensure short and predictable cycle times. Production control strategies based on dispatching rules are very popular in semiconductor manufacturing (cf. the recent survey [55]). But at the same time, scheduling approaches attracted researchers and people from industry working in semiconductor manufacturing for the last two decades (cf. [5], [58] for some older references). This is mainly because of a relatively high degree of automation (compared to other industries) that even 20 years ago allowed for automated real-time data collection and because of the fact that manual production control often leads to strange or unexpected behavior of the systems due to the complexity of the manufacturing process. The well-known book on intelligent scheduling [61] describes several large-scale scheduling prototypes from the semiconductor manufacturing domain. Until recently, full factory scheduling methods seemed to be too costly in comparison to dispatching methods. However, with the recent dramatic increase in computer efficiency full fab scheduling methods have become more competitive. Because of the increasing automation pressure caused by automated material handling systems (AMHS) and new requirements on production control, it seems that scheduling approaches are both promising and necessary in the semiconductor manufacturing domain (cf. [43] for a survey related to scheduling requirements in semiconductor manufacturing). There is a lot of material from academia and also from software vendors related to scheduling in wafer fabs. However, except for the survey paper [53] from the early 1990s and a more current paper [30], there is no current source that reports on the breadth of scheduling problems within semiconductor manufacturing in one place. All the present authors worked in the past and will continue work in the future on different aspects of scheduling for semiconductor manufacturing. In this paper, we will give a concise summary of the different problems and solution techniques as well as comments on problems that need more research efforts in the future. We note that this paper is not a complete review of the vast literature, however we hope to stimulate even more research and some successful real-world implementations in scheduling wafer fabs. The paper is organized as follows. In Section 2, we describe the semiconductor wafer fabrication process briefly. We identify important scheduling problems in Section 3 and discuss solution techniques related to these scheduling problems. Finally, we identify some challenges for future research in Section 4. 2 Semiconductor Manufacturing Process Description A semiconductor chip is a highly miniaturized, integrated electronic circuit consisting of thousands of components. Every semiconductor manufacturing process starts with raw wafers, thin discs made of silicon or gallium arsenide. Depending on the diameter of the wafer, up to a few hundred identical chips can be made on each wafer, building up the electronic circuits layer by layer in a wafer fab. Next, the wafers are sent to Probe, where electrical tests identify any individual die that is not likely to be good when packaged. The bad dice are either physically marked or an electronic map is made of them so that they will not be put in a package. The probed wafers are sent to an Assembly facility where the "good" dice are put into the appropriate package. Finally, the packaged dice are sent to a Test facility where they are tested in order to ensure that only good products are sent to customers. Wafer fab and Probe are often called the "Frontend" and Assembly and Test are often called the "Backend." 193

3 Considering the scale of integration, the type of chip, the type of package, and customer specifications, the whole manufacturing process may require up to 700 single processing steps and up to three months to produce. The four main stages of semiconductor manufacturing are shown in Figure 1. Wafer Fab Probe DAP-3XC Assembly Test Figure 1: Main Stages of Semiconductor Manufacturing Many authors have remarked on the difficulties of semiconductor manufacturing (cf. [2], [42], [50], [53], [55], [58] amongst others). Wafer fabrication has a number of unusual facets that are described below. In a typical wafer fab, there often are dozens of process flows. Each process flow contains processing steps and more than one hundred machines. These machines are expensive, ranging in price from a couple of hundred thousand dollars to over twenty million dollars per tool. The economic necessity to reduce capital spending dictates that such expensive machines be shared by all obs requiring the particular processing operation provided by the machine, even though they may be at different stages of their manufacturing cycle. This results in a manufacturing environment that is different in several ways from both traditional flow shops as well as ob shops. The main consequence of the re-entrant flow nature is that wafers at different stages in their manufacturing cycle have to compete with each other for the same machines. The typical re-entrant flow of a wafer fab is shown in Figure 2. Material Preparation Deposit Film Pattern Film Etch Film Test Figure 2: Re-entrant Flow in Wafer Fabs Furthermore, the nature and duration of the various operations in a semiconductor flow differ significantly. Some operations require 15 minutes or less to process a ob, while others may require over 12 hours. Many of these long operations involve batch processes. In reality, it is not uncommon for one-third of the fab operations to be batch operations. Batch machines tend to off-load multiple obs (1 to 12) onto machines that are capable of processing only one ob at a time. This leads to the formation of long queues in front of these serial machines and ultimately a non-linear flow of products in the factory. The probabilistic occurrence of long tool failures results in large variability in the time a ob spends in process. High variability in cycle times prevents accurate prediction of production cycle times, resulting in longer leadtime commitments. There are some machines, such as implanters, that require significant sequence-dependent setups. If not scheduled well, these tools can become bottlenecks. Finally, some processing steps require an auxiliary resource (a so-called secondary resource), such as a reticle in photolithography, in order to process the ob. Some of these auxiliary resources are quite expensive, so only a very limited number of them are purchased. Therefore, the challenge is to ensure that the machine and the auxiliary resource are available at the same time. 194

4 In modern 300-mm wafer fabs, wafers are transported in front-opening unified pods (FOUP) using an AMHS. Because of the increase in area and weight of the wafers, it is obvious that a manual handling of the wafers has to be eliminated. This fact increases the need for scheduling approaches. Automated material handling is always a critical operation in modern wafer fabs (cf. [1], [23], [33] for more details on AMHS in semiconductor manufacturing). Next, we discuss backend operations. There are usually more types of parts being made in an assembly factory than in a wafer fab, but each part type requires steps instead of One difficulty in modeling these operations is the fact that a ob is often divided into subobs with each sub-ob being sent to the next machine when it completes an operation. Thus, one ob may be being processed across several machines at the same time. Another difficulty is that there is often a very significant amount of setup required to change over from one product type to another. Finally, batching machines are also often present in assembly factories. Test operations have several problems that are difficult to model. First, the sequence of test operations and the test times are not always fixed. These can be changed based on recent product yields, maturity of a product, and such. Second, there are two maor types of equipment used in test operations. These are the test system itself (tester) and the loading mechanism (handler). The tester may have a single or multiple test heads connected to it. The interactions between the tester, the test heads, and the handler can be quite complex to model accurately. Finally, there can be significant sequence-dependent changeover times. In this paper, we will restrict ourselves due to space limitations mainly to the wafer fab part of semiconductor manufacturing. But in a few situations, we will also discuss scheduling problems related to the backend stage. 3 Scheduling Problems and Solution Techniques 3.1 Batching Problems A batch is defined as a group of obs that have to be processed ointly. The completion time of a batch is determined as the completion time of the last ob in the batch. A batch scheduling problem consists in grouping the obs on each machine into batches and in scheduling these batches. Two types of batching problems are considered. The first type is called s-batching. Here, the processing time of a batch is the sum of the processing times of all obs that form the batch. The second type is p-batching. In this case, the processing time of the batch is given by the maximum processing time of obs contained in the batch (cf. [45], [30] for recent surveys related to batching in general and to batching for semiconductor manufacturing respectively). In semiconductor manufacturing, there are some situations where s-batching is important. For example, several scheduling problems related to steppers in the photolithography area lead to s-batching problems. Here, runs are formed. A run is a group of obs of the same mask layer. Therefore, the same reticle is required for processing. Forming a run and processing the obs of the run in a consecutive manner avoids frequent reticle changes. But p-batching is much more important in semiconductor manufacturing. The common assumption is that there exists a fixed batch size B as capacity of the batch machine. Burn-in ovens for semiconductor manufacturing are used to heat-stress test IC chips. Several chips can be tested in a burn-in oven simultaneously, so that a burn-in oven is a batch processing machine. The processing time of each batch is determined by the longest ob processing time among those of all the obs contained in the batch. There are many papers that deal with burnin ovens, for example, the paper [56], where a dynamic programming formulation is coupled with a random key genetic algorithm. Simulated annealing-based heuristics are suggested in [31] for a burn-in scheduling problem. The diffusion furnaces in wafer fabs are an example of batch machines. Here, the obs are assigned to incompatible ob families. While several obs can be processed at the same time, obs of different families cannot be processed together due to the chemical nature of the 195

5 process. The processing time of all obs within one family is the same. Therefore, batching obs with incompatible families is a special case of p-batching. We refer to [3], where the problem Pm batch,incompatible TWT is discussed. We denote by batch, incompatible the p- batching with incompatible families, while the performance measure of interest is minimizing total weighted tardiness TWT : = w max( C d, 0). The notation w is used for the weight of ob, C is used for the completion time, and d for the due date of ob. [3] extends solution techniques for 1 batch,incompatible T presented in [32]. Dispatching rules are used to form batches. Genetic algorithms assign the batches to machines and sequence them. This approach is extended to Pm r,batch,incompatible w T in [35]. This problem is harder because the given release dates r of the obs require a decision whether it makes sense to wait for future obs arrivals in case of incomplete batches or to start a non-full batch. Machine learning techniques applied to batching problems in semiconductor manufacturing are considered in [20], [36]. The problem Pm r,batch,incompatible Lmax where Lmax : = max{ C d = 1, K,n} denoting the maximum lateness, is solved in [27] using genetic algorithms. 3.2 Job Shop Problems A wafer fab can be modeled as a complex ob shop [28], [42]. This type of ob shop contains unrelated parallel machines with sequence-dependent setup times and dedications, parallel batch machines, re-entrant flows, and ready times of the obs. Using the α β γ notation these problems can be expressed by FJ r,s,batch,incompatible, recrc w T, (1) r where FJ denotes the flexible ob shop, s k refers to sequence-dependent setup times, and the term recrc is used for the re-entrant flows. Alternatively, the scheduling problem can be modeled as FJ r,s,batch,incompatible,recrc L. (2) r max Problems of type (1) and (2) have been studied very intensively over the last ten years. Most of the solution approaches are based on disunctive graphs [7]. A good documentation of attempts to solve problem (2) for test facilities can be found in [42]. Several variants of the shifting bottleneck heuristic are used. This heuristic decomposes the ob shop scheduling problem into a set of smaller scheduling problems related to parallel machines. These smaller scheduling problems are called sub problems. Several aspects, like identifying appropriate sub problem solution procedures and determining an appropriate sequence to solve the sub problems, are discussed in a series of papers by Uzsoy and his group (cf., for example, [14], [15], [54]). Mason et al. suggested a modified shifting bottleneck heuristic to tackle problem (1) for wafer fabs in [28]. The performance of this scheme was assessed within a rolling horizon setting using discrete event simulation in [37]. Sub problem solution procedures based on genetic algorithms are suggested. A distributed variant of the shifting bottleneck heuristic for wafer fabs using information from an upper planning layer is discussed in [34]. This distributed 196

6 scheduling scheme is the base for the hierarchically organized multi agent system FABMAS [38]. While very often only single instances were considered, [49] contains the results of a rolling horizon scheme for problem (2). Later, several attempts were made to reduce the number of nodes in the scheduling graph by considering only specific bottleneck machines explicitly. Experiments with this approach for obs shops that include machine breakdowns are presented in [4], [51], [52]. Only little is known on the impact of rescheduling techniques for complex ob shops [29]. A multi-criteria approach for scheduling wafer fabs based on the shifting bottleneck heuristic is suggested in [44]. While some progress was made related to the integration of transportation operations and other generalizations in scheduling research for ob shops (cf. [7] for a documentation of state of the art approaches), it seems that only some first steps into this direction were done in semiconductor manufacturing (cf. [16], [46]). Even the simulation of the base system for manufacturing and for transportation is sophisticated in the case of wafer fabs. But this is a requirement for assessing the performance of rolling horizon schemes. Many current scheduling techniques for large-scale ob shops with a makespan obective are based on metaheuristic search using the disunctive graph formulation [7]. Because of the reentrant flows and different obectives, only initial steps are known to apply such methods to scheduling problems in semiconductor manufacturing [60]. Simulated annealing techniques based on a generalized disunctive formulation for several batch machines and up-and-down stream machines are discussed in [59]. The resulting scheduling software called Batch Optimization Solver (BOS) is designed to solve real-world scheduling problems in the diffusion area of a wafer fab. Beside the global scheduling problems (1) and (2), there are many papers that discuss scheduling approaches for specific machine environments in semiconductor manufacturing. We refer, for example, to [11] where a genetic algorithm is used to schedule obs on furnace machines including sophisticated process conditions. Another example is given by [48] where ant colony optimization approaches are used to schedule obs on a group of machines that is the leading bottleneck in a wafer fab. The use of mixed integer and constraint programming approaches for solving real-world scheduling problems in a wafer fab is described in [6], [19]. Instead of considering the entire scheduling problem, a decomposition into different sub problems is performed before using mathematical programming tools. 3.3 Problems with Secondary Resources As already described in Section 2, secondary resources are an important restriction in semiconductor manufacturing. Secondary resources are typically related to parallel machines. Photolithography steppers that require product and mask layer specific reticles are a typical example for such type of machines. Scheduling heuristics based on dispatching rules for the problem Pm r,aux w C are described, for example, in [12]. Here, we denote by aux the secondary resource. Several heuristics for stepper scheduling based on appropriate modifications of the Apparent Tardiness Cost (ATC) dispatching rule are described in [13]. The scheduling of a single batch processing machine with ob families motivated by burn-in operations in a test facility is discussed in [24]. Load boards are considered as secondary constraints. Several heuristics are presented. 3.4 Multiple Orders per Job Problems The combination of decreased line widths and more area per wafer in 300-mm wafer fabs result in fewer wafers being needed to fill an IC order of a customer. Each wafer fab will have only a limited number of FOUPs as they are expensive. A large number of FOUPs have the potential to cause overload in the AMHS. In addition, some batching tools have the same 197

7 processing times regardless of the number of wafers in the batch. Thus it is not reasonable to assign an individual FOUP to each order. Therefore, 300-mm manufacturers often have the need and the incentive to group orders from different customers into one or more FOUPS to form production obs. These obs have to be scheduled on the various types of tool groups in the wafer fab and processed together. This class of integrated ob formation and scheduling problems are called multiple orders per ob (MOJ) scheduling problems. There is a series of papers from Mason and his group that deal with single and parallel machine MOJ scheduling problems [21], [22], [47]. Metaheuristics, dispatching rules, and column generation techniques are used to solve the MOJ scheduling problems. The special case of a two-machine flow shop MOJ scheduling problem is presented in [25]. 3.5 Scheduling of Cluster Tools Cluster tools combine single-wafer processing modules with wafer handling robots in one closed environment (cf. [26] for a recent survey of cluster tool scheduling). Scheduling of cluster tools is challenging because the cycle time of wafers in a cluster tool depends on the used wafer recipes, cluster tool control and architecture, wafer waiting times, and sequencing [17]. A discrete event simulation tool is used in [17] to determine appropriate cycle times for wafers within cluster tools. Several techniques based, for example, on neural networks and beam search are suggested in [39], [40], and [41]. A simulated annealing approach is discussed in [57]. 4 Future Challenges There are several directions for future research related to scheduling in semiconductor manufacturing. The usage of modern metaheuristics for scheduling wafer fabs globally has to be researched. Furthermore, the impact of rescheduling strategies has to be investigated in much more detail. Future research requires a better incorporation of AMHS decisions into the ob scheduling decision-making process. Algorithms are expected that take various specific properties of modern AMHS into account. It seems that a direct extension of the results presented for related problems in [7] is not straightforward. There is a definite need to better understand the relationship between planning and scheduling decisions for complex manufacturing systems like wafer fabs. Some promising initial steps towards reaching this goal are described in [9]. Here, the interaction of more global and local scheduling decisions is studied. Based on the experiences with the FABMAS multi agent system [38] and the distributed shifting bottleneck heuristic [34], a hierarchical decomposition of wafer fab scheduling problems offers some advantage. However, more theoretical insights are necessary. So far, only little is known on the interaction of Advanced Process Control (APC) and scheduling decisions. However, APC information should definitely impact scheduling constraints and criteria. For instance, scheduling some lots with the same process on a tool might be prioritized based on the requirements for the tool to get data on the process. Finally, very often we find it hard to transfer scheduling results from an academic environment to the shop floor. This is mainly caused by data problems. Therefore, appropriate software representations of our scheduling algorithms are required that can better deal with distributed and with missing data. References 1. Agrawal, G. K., Heragu, S. S., A Survey of Automated Material Handling Systems in 300- mm Semiconductor Fabs, IEEE Transactions on Semiconductor Manufacturing, 19(1), , (2006) 198

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