3D-IC Integration Developments & Cooperations for servicing
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1 Ecole de microélectronique et microsystèmes mai 2011, Fréjus 3D-IC Integration Developments & Cooperations for servicing Kholdoun TORKI CMP 46, Avenue Félix Viallet, Grenoble, France
2 Agenda Introduction & Motivation for 3D-IC Process overview Partnership for MPW runs service 3D-IC Design Platform Conclusion
3 3D-IC Integration : Not a New Story Akasaka, Y., and Nishimura, T., "Concept and Basic Technologies for 3-D IC Structure IEEE Proceedings of International Electron Devices Meetings, Vo. 32, 1986, pp
4 3D-IC Integration : The Other Path for Scaling Source IBM Moore s law by scaling conventional CMOS involves huge investments. 3D IC processes : An opportunity for another path towards continuing the scaling, involving less investments. Like for conventional CMOS, infrastructures are needed to promote 3D-IC integration, making it available for prototyping at reasonable costs.
5 Two Worlds with Different Integration Approaches Monolithic Distributing a whole system across several tiers Heterogeneous Multi layer 3D-IC TSV integrated 3D-IC face to face 3D-IC TSV integrated 3D-IC TSV Stacked Memory Die to Die Integrated package Silicon Interposer to high Integrated MCM Substrate based Module (PCB) Multi-Chip Module Discrete Assembly of Known Good Dies
6 Which Design Methodology? Discrete : 3D packaging, stacked dies, 1- Design a whole system. 2- Split it in subsystems. 3- Place the subsystems as predefined Known Good Dies (IPs). 4- Determine and place the interfaces in between. 5- The system is done Monolithic : 3D-IC Integration 1- Design a whole system. 2- Split it in subsystems. 3- Determine and place the interfaces in between. 4- Generate and Place the subsystems in between the interfaces. 5- The system is done Here comes the difference : The key for a true 3D-IC Integration
7 SiP versus 3D-IC
8 3D-IC Applications
9
10 3D Microelectronics for Physics (FermiLab, IN2P3, INFN, CERN)
11 Large Systems Benefits from 3D-IC Integration "Implementing a 2-Gbs 1024-bit ½-rate Low-Density Parity-Check Code Decoder in Three- Dimensional Integrated Circuits" Lili Zhou, Cherry Wakayama, Robin Panda, Nuttorn Jangkrajarng, Bo Hu, and C.-J. Richard Shi University of Washington International Conference on Computer Design, ICCD, Oct Comparison between 3D and 2D designs Performance Factor (Area * Timing * Power) = 14
12 An Illustration: CPU/Memory Stack R8051 CPU 80MHz operation; 140MHz Lab test (VDD High) 220MHz Memory interface IEEE 754 Floating point coprocessor 32 bit Integer coprocessor 2 UARTs, Int. Cont., 3 Timers, Crypto functions 128KBytes/layer main memory 5X performance 1/10 th Power Source Tezzaron (2004)
13 Some 3D-IC Applications Pixel array for Particle detection (HEP community) (Pixel sensor + Analog + Digital + Memory + high speed I/Os) CMOS Image Sensor (Sensor + Processor + Memory) 3D stacked Memories (Flash, DRAM, etc ) Multi-cores Processor + Cache Memory NoC (Network on Chip) Processor + DRAM + RF + MEMS + Optical communication +
14 Design Methodology 3 D 2.9 D The more design automation is performed on the 3 rd dimension, the more is the 3D-IC Integration. 2.8 D 2.7 D 2.6 D NoC Processor + DRAM + RF + MEMS + Optical communication 2.5 D 2.4 D 2.3 D 2.2 D Multi-Processors + Memory Pixel Sensor (HEP) Simple Imaging Sensor Memory Stack 2.1 D 2 D System Complexity
15 CMC-CMP-MOSIS Collaboration
16
17 Benefits for a global Infrastructure CMC / CMP / MOSIS partnering for 3D-IC process access Stimulate the activity by sharing the expenses for manufacturing. Join forces for the technical support, and dedicate the roles for each partner. Make easier the tech support for local users respectively by each local center. Because there is no standard for the 3D-IC integration, it is urgent to setup an infrastructure making possible a broad adoption of 3D-ICs. That will have a beneficial effect on prices, more frequent MPW runs, and more skilled engineers.
18 CMC-CMP-MOSIS partnering on 3D-IC CMP/CMC/MOSIS partner to introduce a 3D-IC process Grenoble, France, 22 June 2010, CMP/CMC/MOSIS are partnering to offer a 3D-IC MPW service based on Tezzaron s SuperContact technology and GLOBALFOUNDRIES 130nm CMOS. The first MPW run is scheduled to 31 May 2011: - 2-tier face-to-face bonded wafers - 130nm CMOS process for both tiers - Top tier exposing TSV and backside metal pads for wire bonding. A design-kit supporting 3D-IC design with standard-cells and IO libraries is available. Further MPW runs will be scheduled supporting process flavors (multiple tiers beyond 2, different CMOS flavors for different tiers,...) driven by user requirements. Potential users are encouraged to contact CMP for details : cmp@imag.fr
19 CMC - CMP - MOSIS Cooperation CMC supporting Canadian Customers CMP supporting European Customers MOSIS supporting US Customers Each may support other locations
20 Tezzaron 2-Tier Process (130nm CMOS) Process Overview
21 Tezzaron Process Flow for TSV and DBI (using Via Middle process) Starting wafer in 130nm (5 Cu metal layers + 6 th Cu metal as DBI) Source Tezzaron
22 Tezzaron Process Flow for TSV and DBI (using Via Middle process) Cu Cu Cu Cu Cu Cu Cu Cu Cu Cu Cu
23 A Closer Look at Wafer-Level Stacking Oxide Silicon Source Tezzaron Dielectric(SiO2/SiN) Gate Poly STI (Shallow Trench Isolation) W (Tungsten contact & via) Cu (M1 M5) Cu (M6, Top Metal) Super-Contact
24 Next, Stack a Second Wafer & Thin: Source Tezzaron
25 Resulting 2-tier 3D-IC integration TSV and DBI (Via Middle Process) DBIs continuing the stacking Top Tier (10um thickness) Bottom Tier (Handle wafer) Source Tezzaron
26 Resulting 2-tier 3D-IC integration TSV and DBI (Via Middle Process) Bond pad for wire bonding or bump, flip-chip Top Tier (10um thickness) Bottom Tier (Handle wafer) Source Tezzaron
27 3D-IC MPW runs
28 3D-IC MPW Initial Infrastructure First MPW Run organized by FermiLab using an Industrial Process Clustering Manufacturing HEP Labs 3D-IC Potential Users
29 3D Consortium : 1st MPW run Test chips: TX, TY 2.0 x 6.3 mm MPW Full Frame Notice Symmetry about vertical center line Subreticules: A, B, C, D, E, F, G, H, I, J 5.5 x 6.3 mm Top tiers Bottom Tiers Source FermiLab (3D Consortium Meeting)
30 3D-IC MPW Infrastructure CMC-CMP-MOSIS partnering to offer 3D-IC MPW runs Clustering Manufacturing 3D-IC Users In discussion Critical mass will allow frequent MPW runs and low pricing
31 CMP/MOSIS/CMC : 1st MPW run MPW run deadline : May 31 st, 2011
32 3D-IC Design Platform
33 Tezzaron / GlobalFoundries Design Platform The Design Platform is modular. It has all features for full-custom design or semi-custom automatic generation design. PDK : Original PDK from GF + (TSV / DBI) definition Libraries : CORE and IO standard libraries from ARM Memory compilers : SPRAM, DPRAM and ROM from ARM 3D-IC Utilities : Contributions developments embedded in the platform Tutorials, User s setup. All the modules inside the platform refer to a unique variable, making it portable to any site. The installation procedure is straightforward. Support of CDB and OpenAccess databases.
34 Tezzaron / GlobalFoundries Design Platform Design documents included in the platform BacksideBondPads1_1.pdf Tezzaron Backside Bond Pad Rules (rev. 1.1 / 4 June 2009) Bond_Interface_Rules_1_0.pdf Bond Interface Rules (rev. 1.0 / 18 July 2007) MPW100109_Design_Guide_8.pdf MPW Design Guide (rev. 8 / 11 Feb. 2010) SuperContact_Rules_2_11.pdf SuperContact Rules (rev. 2.1 / 29 Jan 2008) mpwmemspec1_5.pdf MPW Memory specifications (rel. 1.5 / 16 Feb. 2010) yi_108_dr001_1t.pdf Release notes of the 130nm CMOS Design Rules Manual (version 1T) yi_108_dr001_1t_oct2010.pdf 130nm CMOS Design Rules Manual (version 1T / Oct. 2010) yi_108_ep004_1d.pdf Release notes of the 130nm CMOS Electrical Parameters (version 1D) yi_108_ep004_rev_1d.pdf 130nm CMOS Electrical Parameters (version 1D / 19 March 2010) Black : GlobalFoundries Design Documents Blue : Tezzaron Design Documents Red : Tezzarom Design guide
35 PDK Tezzaron / GlobalFoundries chrt13lprf_dk009_rev_1d (Version issued in Q1 2011) assura calibre cds_cdb cds_oa doc eldo hercules hspice prep3dlvs skill spectre strmmaptables_arm strmmaptables_encounter assura: FILLDRC LVS QRC calibre: 3DDRC 3DLVS DRC FILLDRC calibreswitchdef hercules: DRC LVS STAR_RCXT
36 Collaborative Work to the Design Platform HEP labs contributing with Programs, Libraries, and Utilities. All included in the Design Platform DBI (direct bonding interface) cells library. (FermiLab) 3D Pad template compatible with the ARM IO lib. (IPHC) Preprocessor for 3D LVS / Calibre (NCSU) Skill program to generate an array of labels (IPHC) Calibre 3D DRC (Univ. of Bonn) Dummies filling generator under Assura (CMP) Basic logic cells and IO pads (FermiLab) Floor-planning / automatic Place & Route using DBIs, and TSVs (CMP) Skill program generating automatically sealrings and scribes (FermiLab) MicroMagic PDK (Tezzaron/NCSU)
37 Virtuoso Layout Editor with 3D layers and verification Virtuoso from Cadence IC TSV Back Metal Calibre Back Pad Assura DBI
38 Customized Menu with some utilities Virtuoso from Cadence IC 6.1.4
39 Utility to change automatically from GF colors to new colors
40 Libraries from Providers and Users Univ. Bonn NCSU ARM IPHC FermiLab GF/TSC
41 ARM / Artisan Digital CORE Libraries
42 ARM / Artisan Digital & Analog IO Libraries
43 IPHC Contribution for 3D-IC IO Libraries Pad shell (or envelop) containing TSV and DBI allowing using the ARM IO libraries in 3D-IC designs
44 IPHC Contribution for 3D-IC IO Libraries Pad shell (or envelop) containing TSV and DBI allowing using the ARM IO libraries in 3D-IC designs
45 IPHC Contribution for 3D-IC IO Libraries Pad shell (or envelop) containing DBI and TSV connecting the pad to the backside bonding pad
46 FermiLab Digital Library Basic custom digital cells and IO pads
47 Virtuoso / Calibre 3D DRC Interactive Menu
48 Virtuoso / Calibre DRC Interactive Menu Setting switches graphically
49 Virtuoso / Calibre LVS Interactive Menu Choosing 2D or 3D LVS
50 True 3D Mask Layout Editor Technology Files fully supported by Tezzaron MicroMagic MAX-3D
51 MicroMagic 3D viewer
52 MicroMagic 3D crossection
53 3D-IC Automatic P&R using DBI and TSV System Level Partitioning 3D Floor-Planning DBI, TSV, IO placement Automatic Place & Route Extraction, Timing Analysis Design exploration at system level Design exploration at the physical level DBI, TSV, and IO placement & optimization Cells and blocks place & route can be done tier by tier To be done for each tier, then combined for back-annotation to the 3D top level system Physical verification 3D DRC, 3D LVS Dummies Filling Similar to the full-custom design flow Final 3D DRC
54 Automatic P&R with Direct Bond Interface - Encounter natively refuses to make the routing for pins on DBIs. - Custom scripts solved the problem. It s a workaround. - The resulting layout is compliant to the Tezzaron DRC, LVS etc DBI array generation + P&R DBI completely routed down to the lower metal layers
55 Automatic P&R with Direct Bond Interface Saving the floor plan for the bottom tier, and apply it for top tier so the automatic Place & Route run the placement and routing taking into account the DBI locations. The place & route for both tiers is optimal for timing, buffer sizing and power performance. This should result in a correct by construction design.
56 Cadence / Encounter v 8.1 Bump Array Generator
57 Cadence / Encounter v 8.1 Signal Bumps Assignment
58 Custom Scripts Enabling Routing on DBIs Placing logical pins on bumps (DBIs), and extract their location. Before After Generating Physical pins from these locations. They can now be used as terminals for routing. Before After
59 Automatic P & R Design Flow (From Floor-Plan to Routed Design) - Std cells Placement - Clock Tree Synthesis Filler Cells Placement - DBIs Placement - TSVs Placement - Obstructions on TSVs - Clock routing - Final routing
60 Clock and all nets routing is enabled on M1-M5
61 Access to the Design-Rules and the Design Platform Customer Request NDA Edition NDA Signed NDA reception Request to access from CMP Web page or by to : cmp@imag.fr The user receive by the NDA + ARM lirary Addendum. The user sign and return by post 2 original signed copies CMP forward to Tezzaron the NDAs. When Tezzaron is OK, they counter-sign and return one copy to CMP. CMP return the copy to the user and give the access to the DRM and Design-Platform. Foundry s Agreement Yes Design kit & Design Rules access
62 Users having access to the Design Platform CPPM, Marseille IPHC, Strasbourg LAL, Orsay LPNHE, Paris IRFU, CEA Saclay LAPP, Annecy-Le-Vieux * ENSTA PARISTECH, Paris * ISEA, Toulouse INFN, Roma INFN, Pavia INFN, Pisa University of Bologna * University of Perugia Italy France Tezzaron Semiconductor, USA FermiLab, USA North Carolina State University, USA MOSIS, USA CMC Microsystems, Canada University of Sherbrooke, Canada + Other centers supported by MOSIS and CMC Not listed here. University of Bonn, Germany University of Barcelona, Spain IMSE-CNM-CSIC, Sevilla, Spain University of Turku, Finland Acreo AB, Norrköping, Sweden New Users Norwegian University, Trondheim, Norway More than 19 Users in Europe
63 Conclusion A very collaborative work has been achieved and still ongoing between the parties CMC, CMP, MOSIS, FermiLab, Tezzaron, HEP Labs, NCSU. A Design Platform resulted from the collaboration. (Industrial CAD vendors just starting addressing the features) First MPW run deadline : May 31 st, 2011 The community is awaiting for new CAD tools dedicated to 3D-IC Integration : + 3D-IC Partitioning : both at the system level and the floor-planning level. + Sign-off tools for 3D-IC Integration : (3D-DRC, 3D-LVS, 3D-Extration)
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