XX1007-QT-EV1. Doubler / GHz. Features. Functional Block Diagram. Description. Pin Configuration. Absolute Maximum Ratings

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1 XX17-QT / GHz Features Integrated Gain, and Driver Stages Single Positive Supply, +V Integrated Bypassing Capacitor +2. dbm Output Saturated Power 3. dbc Fundamental Suppression On-Chip ESD Protection 1% RF, DC and Output Power Testing 3x3mm QFN Package RoHS* Compliant and 26 C Reflow Compatible Description M/A-COM Tech s / GHz GaAs MMIC doubler integrates a gain stage, passive doubler and driver amplifier onto a single device. The XX17-QT has a self-biased architecture requiring a single positive supply (+V) only and integrated on-chip bypassing and DC blocking capacitors eliminating the need for any external components. This device uses M/A-COM Tech s GaAs PHEMT device model technology, and is based upon electron beam lithography to ensure high repeatability and uniformity. The XX17-QT has integrated ESD structures for protection and comes in a low cost 3x3mm QFN package. The device is well suited for Millimeter wave Point-to- Point Radio, LMDS, SATCOM and VSAT applications. Functional Block Diagram Pin Configuration Pin No. Function Pin No. Function 3 RF In 1,2,4,,6,7,8,9 NC 1 RF Out 11,12,14,,16 NC 13 Vd Absolute Maximum Ratings Parameter Absolute Max. Ordering Information Part Number XX17-QT-G XX17-QT-GT XX17-QT-EV1 Package bulk quantity tape and reel evaluation board Supply Voltage (Vd) +6. VDC Supply Current (Id) 3 ma Gate Bias Voltage (Vg) +.3 VDC Input Power (RF Pin) 1 dbm Storage Temperature (Tstg) to +16 ºC Operating Temperature (Ta) - to MTTF Table 1 Channel Temperature (Tch) MTTF Table 1 (1) Channel temperature directly affects a device's MTTF. It is recommended to keep channel temperature as low as possible to maximize lifetime. 1 North America Tel: Europe Tel: India Tel: China Tel:

2 XX17-QT / GHz Electrical Specifications: GHz (fin) (Ambient Temperature T = 2 C) Parameter Units Min. Typ. Max. Output Frequency Range (fout) GHz Input Return Loss (S11) db -. - Output Return Loss (S22) db Fundamental Suppression dbc RF Input Power (RF Pin) dbm Output Power at 8. dbm Pin (Pout) dbm Drain Bias Voltage (Vd) VDC Supply Current (Id1,2,3) (Vd=.V Typical) ma North America Tel: Europe Tel: India Tel: China Tel:

3 XX17-QT / GHz Typical Performance Curves Pout V 4V North America Tel: Europe Tel: India Tel: China Tel:

4 XX17-QT / GHz Typical Performance Curves V V Pin = 1dBm Pin = dbm Pin = dbm -1 4V V -1 4V V V 4V -1 V -1 V North America Tel: Europe Tel: India Tel: China Tel:

5 XX17-QT / GHz Evaluation Board Layout Vd RF in RF out MTTF Tables (TBD) These numbers were calculated based on accelerated life test information and thermal model analysis received from the fabricating foundry. Backplate Temperature Channel Temperature Rth MTTF Hours FITs 7 deg Celsius 192 deg Celsius 126 C/W 3.4 E E+2 Bias Conditions: Vd=.V, Id=2mA North America Tel: Europe Tel: India Tel: China Tel:

6 XX17-QT / GHz Lead-Free Package Dimensions/Layout Handling Procedures Please observe the following precautions to avoid damage: Static Sensitivity Gallium Arsenide Integrated Circuits are sensitive to electrostatic discharge (ESD) and can be damaged by static electricity. Proper ESD control techniques should be used when handling these class 2 devices. 6 North America Tel: Europe Tel: India Tel: China Tel:

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