IBM eserver pseries. September, Revised April IBM Corporation. server. pseries

Transcription

1 server H C R server U6 pseries Revised April 2003 September, 2005

2 Ubicación del p615 en el cosmos de servidores

3 Servidores de IBM zseries The most reliable, mission-critical systems on earth pseries Most powerful, technologically advanced UNIX servers iseries High-performance integrated business servers for mid-market companies xseries Intel-based servers with mainframe-inspired reliability technologies

4 El mercado de servidores UNIX Quarterly UNIX-based Revenue Share 45% 45% 40% 35% 40% 30% 35% 25% 20% 30% 15% 25% 10% 5% 20% 15% 10% 5% Q102 Q202 WW UNIX Server Revenue Share Rolling 4Q Average Q302 Q402 Q103 Q203 Q303 Q403 Q104 Q204 Q304 Q404 Q105 Q205 IBM HP Sun Other Source: IDC Quarterly Server Tracker, 8/05

5 POWER4+: El motor del p615

6 pseries 615 POWER4+ Chip Technology Superescalar. Habilidad para ejecutar hasta 8 instrucciones en paralelo. Superpipelined. Posibilidad de completar cinco instrucciones por ciclo. L1 instruction cache 128K/chip;64K/processor. L1 data cache 64K/chip; 32K/processor. L2 cache 1440K/chip; shared between processors). POWER4+ microprocessor D I L3 Cache >1GHz CPU L3 Controller L3 Directory Memory >1GHz CPU Shared L2 Cache Fabric Controller Distributed Switch Processor local bus I/O Bus D I

7 pseries 615 POWER4+ Chip Technology Each processor contains two FXUs (fixed point units) two FPUs (floating point units) two load/store units a branching unit a CR (condition register) unit

8 POWER Microprocessor Roadmap POWER microns 1.0 to 1.3 GHz Core Shared L2 Distributed Switch 2001 Distributed Switch Shared L2 LPAR Autonomic computing Chip multiprocessing GHz Core POWER microns 1.2 to 1.9 GHz Core Shared L2 Distributed Switch 1.2 to 1.9 GHz Core Larger L2 More LPARs High-speed Switch 0.13 microns POWER5 >> GHz Core Shared L2 Distributed Switch microns >>> GHz Core GHz Core Shared L2 Distributed Switch >>> GHz Core way SMP Sub-processor partitioning Enhanced Distributed Switch Enhanced core parallelism Improved floating-point performance Faster memory environment Dynamic firmware updates

9 POWER : The Most Scaleable Architecture POWER5 POWER2 PPC 603e PPC 401 POWER3 PPC 750 PPC 405GP POWER4 POWER4+ PPC 750CXe PPC 750FX PPC 440GP PPC 750GX PPC 970FX PPC 440GX Servers Desktop Games Embedded Binary Compatibility

10 Anatomía del p615

11 Internal Structure of p615 Rack Model Six hot-plug PCI-X slots: Three long 64-bit 133 MHz 3.3v One short 64-bit 133 MHz 3.3v Two short 32-bit 66 MHz 3.3v Service processor Hot-plug power supplies (one redundant optional) 3 hot-plug fans (redundancy) server H C R U6 pseries Server planar board contains: Two 4-packs (separate backplanes) hot-swappable Ultra320 SCSI disks 1st four-pack standard Three media bays Op-panel Two slimline One standard RJ-48 connector (when in use, pre-empts the S1 serial port on rear) One or two GHz or 2-way 1.45 GHz POWER4+ processors, 1.5MB L2 Cache, 8MB L3 Cache, 1 to 16GB DDR Chipkill memory, Three serial ports, two optional HMC ports, keyboard, mouse and parallel ports 10/100 and 10/100/1000 (1 Gbps) Ethernet ports

12 H C R U6 pseries IBM eserver pseries Rear View of p615 Rack Model server server Two hot-plug AC power supplies with dual isolated line cords Parallel Three serial ports (S1, S2, S3) Mfg. Diagnostic port (not for client use) S2 S3 Rack indicator light port S1 HMC 1 HMC 2 10/100 Ethernet 10/100/1000 Ethernet Six hot-plug PCI-X slots: Three long 64-bit 133 MHz 3.3v One short 64-bit 133 MHz 3.3v Two short 32-bit 66 MHz 3.3v

13 p615 Memory Quad Positioning Main memory ranges from 1GB to 16GB ECC DDR SDRAM. Memory is configured in two quads on the planar board, and is pre-balanced by design for optimal performance with each quad split between two synchronous memory interface (SMI) controllers. Plan ahead to reach desired maximum memory to avoid discarding memory. 1GB quad = 4 X 256MB DIMMs 2GB quad = 4 X 512MB DIMMs 4GB quad = 4 X 1GB DIMMs 8GB quad = 4 X 2GB DIMMs SMI L3 Shared L2 Quad 1 Quad 2 SMI Distributed switch

14 pseries 615 Server Peak Bandwidth per 1.2 GHz 2-way Chip 12.8GB/sec (= 2 x 16 1/3 Clock Speed) For 2-way chip Shared L2 L3 6.4GB/sec (= four 8-byte 200 MHz) M E M O R Y 1 to 16GB Distributed switch GX Bus 3.2GB/sec (= dual 4-byte 1/3 Clock Speed) Six PCI-X slots I/O Hub 2GB/sec

15 pseries 615 Server Peak Bandwidth per 1.45 GHz 2-way Chip 15.5GB/sec For 2-way chip Shared L2 L3 6.4GB/sec M E M O R Y 1 to 16GB Distributed switch GX Bus 3.9GB/sec Six PCI-X slots I/O Hub 2GB/sec

16 RAS (Fiabilidad, Disponibilidad y Servicialidad)

17 IBM pseries H C R U6 pseries server server H C R U6 pseries 24x7 IBM eserver pseries POWER4+ Reliability Across the Product Line pseries server Mainframe-inspired RAS Reliability, Availability and Serviceability Self- Protecting Self- Configuring Self- Optimizing Self- Healing server First Failure Data Capture DDR ECC Chipkill memory Bit-steering/redundant memory Memory soft scrubbing Redundant power, fans Dynamic Processor Deallocation Deallocate PCI-X bus, L2/L3 cache Persistent memory deallocation Hot-plug PCI-X slots, fans, power Internal LED diagnostics Hot-swappable disk drives

18 First Failure Data Capture Technology CPU L1 Cache L2/L3 Cache Error Checkers Fault Isolation Register (FIR) (unique fingerprint of each error captured) Service Processor Old Failure Recreate Strategy Run diagnostic test cases during service call Repair based on test case symptom Questionable correlation to original problem Development focus on improved test cases Open service action plan if failure not recreated Test cases used to try to isolate failures and verify correct operation Disk Memory Log Error Nonvolatile RAM Reliably identify each failing component, reducing costly downtime First Failure Data Capture: an IBM Exclusive Specialized hardware designed to capture failure data at time of failure Repair based on root-cause analysis Direct correlation to original client problem Engineering focus on built-in error detection and capture Service action plan driven by captured failure information Test cases used to only to verify correct operation

19 Start Off With Quality-based Design Fault Avoidance Designing extra quality into system to keep errors from ever happening Mainframe-class components and technologies - Reduced power consumption, cooler operating temperatures for increased reliability

20 ECC Memory Integrity and Availability Memory scrubbing for soft single-bit errors that are corrected in the background while memory is idle, to help prevent multiple-bit errors. Failing memory bit steered to spare memory chip Chipkill X X... Dynamically reassign memory I/O via bit-steering if error threshold is reached on same bit Spare memory chip Scatter memory chip bits across four separate ECC words for Chipkill recovery Bit-scattering allows normal single bit ECC error processing, thereby keeping system running with a Chipkill failure. Bit-steering allows memory lines from a spare memory chip to be dynamically reassigned to a memory module with a faulty line to keep system running. If all bits are used up on the spare memory chips, and threshold is reached, the Service Processor will be invoked to request deferred maintenance at a time acceptable to client.

21 Built-in Redundancies for Non-stop Operation N+1 Redundancy Use of redundancy to remain operational with full resources Redundant spare memory chips Redundant fans - Fans will speed up to try to compensate for failed fan Redundant power supplies (optional)

22 p615 PCI Bus and Card Error Recoveries PCI-X Controller X Problem with damaged connection results in PCI-X bus error - That particular slot is varied offline by system - All other slots remain active - System stays operational without the slot active - If PCI card is damaged, replace with new one - If slot is damaged, plan for maintenance at client s convenience

23 Replacement of Parts While System Runs Concurrent Maintenance Online hot-plug of defective electromechanical components keeps system operational Disk drives Cooling fans Power subsystems PCI, PCI-X adapter cards

24 Quicker Service for Client Convenience Service Productivity Increasing service productivity means more client uptime Internal LED diagnostics identify components that require service LEDs on I/O provide status of PCI-X slots and disk drives for power, hot-swap and need for service

25 Sistemas Operativos

26 server H C R U6 server pseries pseries server IBM eserver pseries AIX 5L & Linux AIX Linux Servers AIX Hypervisor Linux Native 64-bit Linux High performance POWER4 SMP, LPAR, Clusters Proven, reliable pseries Surprisingly affordable compared to Intel SMPs Standard Linux APIs in AIX Common Functionality Interoperability Testing AIX Toolbox for Linux Apps - Linux development environment on AIX Run Linux and AIX on the same pseries server Workload Consolidation - Linux for Infrastructure, AIX for Database Server Consolidation - Develop, Test, Production Competitive Consolidation

27 Referencias

28 For more details, see the POWER4 System Microarchitecture white paper at 1.ibm.com/servers/eserver/pseries/h ardware/whitepapers/power4.html (or search for "power4 architecture" in the Search window at

29 Y ya está... (a no ser que tengais más preguntas)