An AreaEfficient Architecture of ReedSolomon Codec for Advanced RAID Systems MinAn Song, IFeng Lan, and SyYen Kuo


 Lydia Hampton
 3 years ago
 Views:
Transcription
1 An AreaEfficient Architecture of Reedolomon Codec for Advanced RAID ystems MinAn ong, IFeng Lan, and yyen Kuo Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan Abstract In this paper, a simple codec algorithm based on Reed olomon (R) is proposed for erasure correcting in RAID level 6 systems. Unlike conventional R, here this scheme with a mathematical reduction method, called Reduced taticchecksum Table Approach, could improve coding performance. We used Reed olomon which are designed according to characteristics of advanced RAID systems to handle two disk failures in RAID system. Also, this scheme performs all computations with only simple exclusiveor (XOR) operators just the same as EvenOdd. This new XORbased R could adapt to implementation in terms of improving reliability and flexibility.. Introduction In storage systems, especially for large disk arrays, reliability is getting critical while storage systems scale up. In [], it has been demonstrated that disk failures would be a daily event in petabytescale file systems. o, how to improve the capability of detecting or even correcting failures has been a significant issue for large storage systems. RAID systems which could be classified from level to 6 are commonly used to achieve this issue. Unlike other levels, RAID level 6, or socalled RAID 6, not only provide correcting capability, but also could recover at least two disk failures simultaneously. Usually each specific algorithm in RAID 6 performs a particular parities distribution []. Over the last two decades, lots of erasurecorrecting algorithms in RAID 6 have been proposed such as EvenOdd [3], Reedolomon (R) [], and X [5]. R code, a very popular error control code, has been studied in various applications, especially in communication systems [6]. Also, researchers have suggested some R based solutions to avoid hazards happening in RAIDlike systems [7], but those schemes might not be suitable to meet the desire of recovering system as quick as EvenOdd. Therefore, in this paper, we present an XORbased R codec scheme, which uses a reduced staticchecksum table approach, to manipulate the erasuresonly hazard. Basically, in this new scheme, it is similar to the conventional R codec algorithm [] that involves pipeline procedure, which consists of yndrome Calculation (C), Key Equation olver (KE), Chien earch (C), and Forney Algorithm (FA), but without involving the portions of either KE or C. Both KE and C are used to locate errors and need extra cost of finite field operators. For the erasureonly RAID system, system controller is not necessary to locate such errors since the individual disk devices have their own errorcontrol coding mechanisms to recover from errors []. Moreover, usually in large disk arrays, failures of a single storage device could be detected by the storage system controllers and then could be marked as well []. ince device failures can be marked as erasures, erasurecorrecting are usually employed to achieve the information recovery, the failed in disks can be recovered and system still can work as usual without broken. Compared with the traditional R codec scheme, a simpler scheme is proposed in this paper in terms of less cost, improving flexibility and reliability. The rest of this paper is organized as follows. ection describes general ideas in our encoding algorithm for the erasureonly RRAID system and the main feature of our scheme, called reduced staticchecksum table approach, is suggested as well. Our decoding approach will be shown in ection 3. ection gives results of performance analysis and also a comparison in the number of XOR operations with the EvenOdd, the traditional RRAID structure, and the XORbased R code as well. The Hardware implementation of the proposed R decoderencoder is described in ection 5. Finally, ection 6 gives the conclusions.. RRAID Encoder The encoding procedure in our scheme not only follows the rules of a mapping with systematic, but also builds a lookup table with an aspect of the constant multiplier. A mapping, in most R encoders, and the encoder usually generates systematic, namely, message bits of a symbol could be presented explicitly in its corresponding codeword. Equation cw( x) b( x) n k m ( x ) x shows a result after applying the systematic coding method, where cw(x), b(x), and m(x) are codeword, checksum and message respectively. W is the codeword length in the R code [8]. If W=, there could be checksum drives and drives in this system, i.e. b(x)={c, C, C3, C} and m(x)={d, D, D3,., D, D}. This research was supported by the Ministry of Economics, Taiwan under contract number 93EC7A86 Proceedings of the 5 th International Conference on Parallel and Distributed ystems (ICPAD'5) $. 5 IEEE
2 . Basic cheme in R Encoding The R code is a class of linear block [], so its computation must satisfy a linear property, that is to say, we can treat each symbol (drive) independently. In other words, any change in each drive would affect checksum symbols (drives) independently. Here, we deduce the linear property of our RRAID model using constant multipliers as follows: b(x) x m(x) mod g(x) k  x (m m x m x m k x ) mod g(x) (x m mod g(x)) (x m mod g(x)) n  (x m k  mod g(x)) m (x mod g(x)) m (x mod g(x)) n  m k  (x mod g(x)) () For that reason, the effect of each symbol (drive) could be computed separately to see how it works to checksum symbols first. Then the complete checksum symbols must be computed by accumulating the effects of all independent drives. Algorithm for Building Checksum ymbols (Encoding Procedure): tep. Premultiply (or shift) the message polynomial m(x) by x nk. tep. Construction of a staticchecksum table: Computing the item: [m i x nk mod g(x)], where each m i equals to multiplicative identity: in GF(x), would know what the effect is in each location (drive). tep 3. By using the table we built in tep, checksum symbols b(x) would be obtained by multiplying all values of staticchecksum table by the practical value of m(x). It nk can be presented as m ( x mod g( x)) m ( x n k mod g( x)).we are able to easily apply the constant multiplier to operate all computations after constructing the staticchecksum table, because all values of the constant table from tep are fixed.. Reduced taticchecksum Table Approach The encoding process is still very crucial due to operating too many XOR gates, even after constructing the previous lookup table. Therefore, a further work to reduce the number of required XOR gates during the encoding process is proposed in this paper. In case of GF( ), for example, applying the aspects of constant multipliers with only a variable could build a table, called constantmultiplier coefficient table ( abbreviated as CMC table), 3 as Table, where A a a a 3 a is the variable with coefficients a ~ a, and a ' ~ ' a are coefficients of A which is generated after being z multiplied by, where z = : Table. The constant multiplier coefficient table Now, if we take a generator polynomial: g ( x ) ( x )( x ), x ( ) x x x with a capability to tolerate up to two erasures, the checksums b(x)=c x+c could be shown as Table.In order to obtain the sixth column, which indicates as the number of XOR operations after the reduction, in Table, our approach consists of following steps: tep. For each location of the staticchecksum table, first, two values of checksums, C and C, are marked. And then in the CMC table, i.e. Table, each marked value could be represented as parts of a single row. tep. Comparing each part of the two rows, there might be some common terms in both rows, which we marked in tep. If so, we could reduce half of these common terms until there is no more common term between both rows. tep 3. Finally, the value of the sixth column in Table can be accumulated by the rest of XOR operations in each part of the two marked rows in Table. Proceedings of the 5 th International Conference on Parallel and Distributed ystems (ICPAD'5) $. 5 IEEE
3 Table. The reduced staticchecksum table with m(x) = = 9 = 7 C= ( * ) 7 ( * ) C= ( * ) 9 ( * ) Figure illustrates placement in our RRAID system, where C and C are checksum drives, DD3 are drives, and for each column, values of the second row are corresponding symbols to their binary values. For instance, to reduce location D in the tatic Checksum Table tep. C = 5 and C =, therefore, we marked the rows A* 5 and A*. tep. Through comparing the following two marked rows, as we can see, a3 a, a 3 a a a, and a a 3 are all the common terms between the two rows. Hence, after applying this approach, the total XOP operations could be reduced by 5 XOR operations. a, tep 3. The number of required XOR operations after processing step is 5 = 9. Besides, this scheme applies the shortened code method as well to achieve a better performance on coding process []. With this method, active drives are placed on some exact locations first. This disk location arrangement is based on which disk costs fewer XORgates after our reducing approach. That is to say, in the case of Table, to reach higher performance of computations, the locations must be arranged with the order, D8, D3, D, D9, etc. Let s assume that a message polynomial, m(x)= x, has to be stored into an empty RRAID in GF( ). And all in checksum drives could be computed as follows: B, from the location D, x of the Table, we could put * and * into two checksum drives separately. imilarly, by, from D5, x 6 in Table, the stored of the two checksum drives are * 7 and * 9. Therefore, values stored in the two checksumdrives after the above processes are: Figure. Data allocation in RRAID ystem with hortened Code method 3. RRAID Decoder In this section, two cases of decoding algorithm are discussed over GF( ), and they are carried out by a solving equations method, called crammer rule, directly. 3. ingle Failed Disk We take to be one of the roots with consecutive powers in our generator polynomial, i.e., g(x)=(x )(x ). Therefore, in the case of single failed disk condition, the decoding would be performed as easily as the parity scheme of the RAID level 5. From the equation: Failed Drive= =(All Normal Drives), recovering the failed disk needs only to do XOR operations in the rest of active disks together. Assuming that only the drive D has been erased as Figure. Figure. A RAID with only a failed disk The original information of D could be recovered as: D(,)=C(,)+C(,)+D(5,)=++= D(,3)=C(,3)+C(,3)+D(5,3)=++= D(,)=C(,)+C(,)+D(5,)=++= D(,)=C(,)+C(,)+D(5,)=++=. 3. Two Failed Disks at the ame Time In this case, in order to recover two disks which simultaneously fail, the decoding procedure in our scheme could be treated as solving a simultaneous linear equation Proceedings of the 5 th International Conference on Parallel and Distributed ystems (ICPAD'5) $. 5 IEEE
4 with two unknown variables. Here the matrix form of this equation is as follows. i j A B, where i and j are both the very positions of the two failed disks in this condition, and then syndrome: n kz cw is computed from all normal drives. k z Z By the crammer rule, the two variables, A and B, could be represented as follows respectively: A j, i j B. () i i j Furthermore, applying the same idea of the CMC table to build a table fulfilled with inverseelements of i j ( ) in advance would be more efficient. This table can avoid the extra cost of implementation on designing an ALU. In the circuit implementation: could be computed through XOR all the normal drives. For the syndrome, if the implementation of s hardware must be an VLI chip, it could share the same hardware with the encoder designed, both of them could share the same circuit of the multiplier.. Results and Comparisons In order to demonstrate how the encoding performance of our XORbased R algorithm is, we implement both CMC table and reduced staticchecksum table in GF( 8 ) to count the total number of XOR operators. Besides, a disk drive set {7,, 3, 7, 3, 9, 3,, 3} is our experimental example. Here, Figure 3 shows corresponding curves to Table 3. Table 3. # of XOR gates while encoding with the XORbased R, the conventional R and the EvenOdd # of Disk Drives Even Odd XOR based Reed olomon Conventional Reedolomon than what the XORbased R code does. However our approach indeed needs less XOR operators than the conventional R did in [3]. Figure 3. Curves plotted by the # of XOR gates while encoding with the XORbased R, the conventional R and the EvenOdd code. Moreover, here Figure shows that traditionally Even Odd need to be implemented by coding through a 3 dimension structure while our algorithm can be easily implemented through a dimension array structure. For Figure, if there is a byte changed, we need to deal with eight codewords from Page to Page 7. Therefore, the update might be an overhead to EvenOdd, but it does not happen in our scheme because we chose 8 bits to be the length of a codeword in the D array structure. Figure. The 3dimension structure of EvenOdd implementation ( n 8 ) In order to compare R with EvenOdd, we use EvenOdd proposed in [3] directly, which en (m) bytesdisk and m drives, and the estimated number of this EvenOdd code is 8 (m m ). That is there are m*(m) bytes will be encoded. In order to process the same amount of, we multiply the above by (m) directly, and the amount of is also equal to m*(m) bytes. The comparisons are listed as follows. From both Table 3 and Figure 3, we can see, the Even Odd perform a more efficient encoding capability Proceedings of the 5 th International Conference on Parallel and Distributed ystems (ICPAD'5) $. 5 IEEE
5 Figure 5. The number of XOR gates to encode m*(m) bytes Apparently, the calculating speed of R code is slower than EvenOdd. If there are 5 to 53 hard disks, the calculation amount is from. to.75. However, the main point mentioned here is that from the coding framework, Reed olomon proposed in the paper can process in parallel. That is because the encoding process of the proposed Reed olomon Code can calculate the effects of each drive to checksum drives respectively. Finally, we add the effects of each drive to checksum drives. Hence, the framework is suitable for parallel processing. Therefore, calculating process can be speeded up and time can be saved Odd Reed olomon MD code Yes Yes Calculating Medium Easy Complexity Encoding Mapping is easy and intuitive EvenOdd Mapping is done in tree dimension, hard to do addressing. Decoding Processes are simple large amount of buffers (memory) Flexibility Yes Yes Frameworks Parallel process Multiarray parallel process Table. A comparison sheet between R code and Even Update complexity Faulttolerant capability # of checksum > drives Design free Only 5. Hardware Implementation of This R RAID Codec In this section, we use Altera tratix FPGA Device (EPF8C5) to implement R Codec, Figure 6. is the Functional Diagram. fail fail_no Codec Encoder C C Decoder _A _A C _B C fail fail_no Figure 6. GF( ) Codec functional diagram 5. The Encoder Block In the encoder block, we create a module (a multiplication table ) that will help to generate the checksum ( C, C) as soon as there is any written to Hard Drive. D D D D3 C C_d_new C_d3_new C C_d_new C_d3_new 5. The decoder block Xor Xor C_d_new C_d_new C_d3_new C_d3_new Figure 7. Encoder block diagram The decoder block includes two sub modules: (a) FM_decoder: It is a tate Machine to control the path for even one or two Hard Drive errors. (b) path: The path is the function(pgz C C C C C C Proceedings of the 5 th International Conference on Parallel and Distributed ystems (ICPAD'5) $. 5 IEEE
6 algorithmic) to calculate the correct with C,C and other correct Hard Drive Data when there is any Hard Drive Data failed. _A : The correct of the failed hard drive; _A, _AB: The two correct of the failed hard drives. fail C C fail_no FM_decoder en_i en_a en_i en_j en_ en_ en_a en_b path _A _A _B _A _A _B Figure 8. Decoder block diagram During the FPGA implementation, we will use the EDA Tools in Table 5. Table 5. EDA Tools Tool Name Text Editor Modelim Quartus II RTL Coding Function Description Function and Timing imulatiom Altera FPGA Compiler for ynthesis, P&R,Timing Analyzing and Power Estimation wr en no[] no[] no[] no[3] [] [] [] [3] fail[] fail_no[] fail no[] fail[] fail_no[] fail no[3] C[] C[] C[] C[] C[] C[3] C[] C[3] Fig 9. FPGA floorplan Table 6. Pin name description Pin name IO Description I ystem Clock I Reset ignal I Write Enable ignal A[] A[] A[] A[3] A[] A[] A[] A[3] B[] B[] B[] B[3] During the FPGA Implementation, we will use the EDA Tools in Table5. The detail is described as follows: (a) RTL Coding: We use Verilog HDL to create all the design files. (b) Function imulation: Use Modelim to verify the Codec design function. (c) ynthesis and P&R: Use QuartusII to map the Verilog HDL format to Altera Atmos format netlist, and perform the Timing Analyzing. (d) Timing imulation: Use Modelim to verify the Codec design Timing. (e) Power Estimation: Use QuartusII to estimate the internal and IO power. I Write Done ignal I Hard Drive No for Write Data I Data for Write to Hard Drive fail I Hard Drive Fail ignal fail_no I Failed Hard Drive No C O Encoder Checksum Data C O Encoder Checksum Data _A O Decoder Recovery Data _A O Decoder Recovery Data _B O Decoder Recovery Data Proceedings of the 5 th International Conference on Parallel and Distributed ystems (ICPAD'5) $. 5 IEEE
7 Table 7 ummarizes chip characteristics and clarifies whether the structure owns the feature of power efficiency. Device : Table 7. Chip characteristics Total logic elements,5 Actual Time imulation End Time imulation Netlist ize EPF8C MHz ( period = 9.3 ns ) 9. us Total Number of Transitions Total Power 5.3 imulation Waveform 576 nodes.8 mw (A) Encoder If m(x) = Write D: ; D5:. Then results are C: ; C:, as shown in Figure Figure. Encoder simulation waveform (B) Decoder If 5th Hard Drive (Drive_NO:) fail, then the encoder will calculate the correct (DATA_A:) with all other Hard Drive and C, C. as shown in Figure. Figure. Decoder simulation waveform 6. Conclusion In this paper, we proposed an XORonly RRAID algorithm with two auxiliary tables, the CMC table and the reduced staticchecksum table, which not only constructing the XORbased R algorithm, but also speeding our scheme up. The above features also make those advanced RAID systems with our scheme be carried out by merely using regular industrial RAID level 5 controllers, which are capable of performing the XOR calculations very well. Therefore a lower cost controller could be applied in our RAID 6 algorithm in stead of a specific designed controller, which usually cost a lot, needed in other RAID 6 algorithms. We proposed an XORonly RRAID algorithm to optimize the coding circuits is suitable for RAID ystems applications where the accuracy, power, speed, and area issues are crucial. References [] Qin Xin, E.L. Miller, T. chwarz, D.D.E. Long,.A. Brandt, W. Litwin, Reliability mechanisms for very large storage systems, Mass torage ystems and Technologies, 3. (MT 3). Proceedings th IEEEth NAA Goddard Conference, 7 April 3, pp [] P.M. Chen, E.K. Lee, G.A. Gibson, R.H. Katz, and D.A. Patterson, RAID: HighPerformance, Reliability econdary torage, ACM Computing urveys, June 99, pp [3] M. Blaum, J. Brady, J. Bruck, and J. Menon, EVENODD: An efficient scheme for tolerating double disk failures in RAID architectures, IEEE Transactions on Comput., Feb. 995, pp. 9. [] Irving. Reed, Xuemin Chen, ErrorControl Coding For Data Networks, Kluwer Academic Publishers, 999. [5] L. Xu and J. Bruck, Xcode: MD array with optimal encoding, IEEE Transactions on Information Theory,, Jan. 999, pp [6] Telemetry Channel Coding, Recommendation for pace Data ystems tandards, CCD.B3, Blue Book, Issue 3, May 99. [7] J.. Plank, Correction to the 997 Tutorial on Reed olomon Coding, Technical Report UTC35, University of Tennessee, April, 3. [8] J.. Plank, A tutorial on Reedolomon coding for faulttolerance in RAIDlike systems. oftware Practice& Experience, eptember 997, 7(9):995. [9] T.K. Truong, J.H. Jeng, T.C. Cheng, A New Decoding Algorithm for Correcting Both Erasures and Errors of Reedolomon Codes, IEEE Transactions on Communications, March 3, pp [] D.V. arwate, N. R. hanbhag, Highpeed Architectures for Reedolomon Decoders, IEEE Transactions on VLI,, pp [] Lihao Xu, Highly Available Distributed torage ystems, Ph.D. Dissertation, 999. Proceedings of the 5 th International Conference on Parallel and Distributed ystems (ICPAD'5) $. 5 IEEE
Distributed Storage Networks and Computer Forensics
Distributed Storage Networks 5 Raid6 Encoding Technical Faculty Winter Semester 2011/12 RAID Redundant Array of Independent Disks Patterson, Gibson, Katz, A Case for Redundant Array of Inexpensive Disks,
More informationAlgorithms and Methods for Distributed Storage Networks 5 Raid6 Encoding Christian Schindelhauer
Algorithms and Methods for Distributed Storage Networks 5 Raid6 Encoding Institut für Informatik Wintersemester 2007/08 RAID Redundant Array of Independent Disks Patterson, Gibson, Katz, A Case for Redundant
More informationTheoretical Aspects of Storage Systems Autumn 2009
Theoretical Aspects of Storage Systems Autumn 2009 Chapter 2: Double Disk Failures André Brinkmann Data Corruption in the Storage Stack What are Latent Sector Errors What is Silent Data Corruption Checksum
More informationA ReedSolomon Code for Disk Storage, and Efficient Recovery Computations for ErasureCoded Disk Storage
A ReedSolomon Code for Disk Storage, and Efficient Recovery Computations for ErasureCoded Disk Storage M. S. MANASSE Microsoft Research, Mountain View, California, USA C. A. THEKKATH Microsoft Research,
More informationTowards High Security and Fault Tolerant Dispersed Storage System with Optimized Information Dispersal Algorithm
Towards High Security and Fault Tolerant Dispersed Storage System with Optimized Information Dispersal Algorithm I Hrishikesh Lahkar, II Manjunath C R I,II Jain University, School of Engineering and Technology,
More informationSTAR : An Efficient Coding Scheme for Correcting Triple Storage Node Failures
STAR : An Efficient Coding Scheme for Correcting Triple Storage Node Failures Cheng Huang, Member, IEEE, and Lihao Xu, Senior Member, IEEE Abstract Proper data placement schemes based on erasure correcting
More informationExample: Systematic Encoding (1) Systematic Cyclic Codes. Systematic Encoding. Example: Systematic Encoding (2)
S72.3410 Cyclic Codes 1 S72.3410 Cyclic Codes 3 Example: Systematic Encoding (1) Systematic Cyclic Codes Polynomial multiplication encoding for cyclic linear codes is easy. Unfortunately, the codes obtained
More informationA Tutorial on ReedSolomon Coding for FaultTolerance in RAIDlike Systems
A Tutorial on Reedolomon Coding for FaultTolerance in RAIDlike ystems James lank Technical Report C96332 Department of Computer cience University of Tennessee IMORTANT The information dispersal matrix
More informationtechnology brief RAID Levels March 1997 Introduction Characteristics of RAID Levels
technology brief RAID Levels March 1997 Introduction RAID is an acronym for Redundant Array of Independent Disks (originally Redundant Array of Inexpensive Disks) coined in a 1987 University of California
More informationMemory and Programmable Logic
Chapter 7 Memory and Programmable Logic 7 Outline! Introduction! RandomAccess Memory! Memory Decoding! Error Detection and Correction! ReadOnly Memory! Programmable Devices! Sequential Programmable Devices
More informationE cient parity placement schemes for tolerating up to two disk failures in disk arrays
Journal of Systems Architecture 46 (2000) 1383±1402 www.elsevier.com/locate/sysarc E cient parity placement schemes for tolerating up to two disk failures in disk arrays NamKyu Lee a, SungBong Yang a,
More informationImplementation of Full Parallelism AES Encryption and Decryption
Implementation of Full Parallelism AES Encryption and Decryption M.Anto Merline M.ECommuication Systems, ECE Department K.Ramakrishnan College of EngineeringSamayapuram, Trichy. AbstractAdvanced Encryption
More informationSimulation & Synthesis Using VHDL
Floating Point Multipliers: Simulation & Synthesis Using VHDL By: Raj Kumar Singh  B.E. (Hons.) Electrical & Electronics Shivananda Reddy  B.E. (Hons.) Electrical & Electronics BITS, PILANI Outline Introduction
More informationA Tutorial on ReedSolomon Coding for FaultTolerance in RAIDlike Systems
A Tutorial on ReedSolomon Coding for FaultTolerance in RAIDlike Systems James S Plank Department of Computer Science University of Tennessee February 19, 1999 Abstract It is wellknown that ReedSolomon
More informationThe implementation and performance/cost/power analysis of the network security accelerator on SoC applications
The implementation and performance/cost/power analysis of the network security accelerator on SoC applications RueiTing Gu grating@eslab.cse.nsysu.edu.tw KuoHuang Chung khchung@eslab.cse.nsysu.edu.tw
More informationCyclic Codes Introduction Binary cyclic codes form a subclass of linear block codes. Easier to encode and decode
Cyclic Codes Introduction Binary cyclic codes form a subclass of linear block codes. Easier to encode and decode Definition A n, k linear block code C is called a cyclic code if. The sum of any two codewords
More information= 2 + 1 2 2 = 3 4, Now assume that P (k) is true for some fixed k 2. This means that
Instructions. Answer each of the questions on your own paper, and be sure to show your work so that partial credit can be adequately assessed. Credit will not be given for answers (even correct ones) without
More informationInternational Association of Scientific Innovation and Research (IASIR) (An Association Unifying the Sciences, Engineering, and Applied Research)
International Association of Scientific Innovation and Research (IASIR) (An Association Unifying the Sciences, Engineering, and Applied Research) ISSN (Print): 22790020 ISSN (Online): 22790039 International
More informationChapter 7 Memory and Programmable Logic
1 Chapter 7 Memory and Programmable Logic 2 71. Introduction There are two types of memories that are used in digital systems: Randomaccess memory(ram): perform both the write and read operations. Readonly
More informationAn Introduction to Galois Fields and ReedSolomon Coding
An Introduction to Galois Fields and ReedSolomon Coding James Westall James Martin School of Computing Clemson University Clemson, SC 296341906 October 4, 2010 1 Fields A field is a set of elements on
More informationData Storage  II: Efficient Usage & Errors
Data Storage  II: Efficient Usage & Errors Week 10, Spring 2005 Updated by M. Naci Akkøk, 27.02.2004, 03.03.2005 based upon slides by Pål Halvorsen, 12.3.2002. Contains slides from: Hector GarciaMolina
More informationEMC CLARiiON RAID 6 Technology A Detailed Review
A Detailed Review Abstract This white paper discusses the EMC CLARiiON RAID 6 implementation available in FLARE 26 and later, including an overview of RAID 6 and the CLARiiONspecific implementation, when
More informationModule 3. Data Link control. Version 2 CSE IIT, Kharagpur
Module 3 Data Link control Lesson 2 Error Detection and Correction Special Instructional Objectives: On completion of this lesson, the student will be able to: Explain the need for error detection and
More informationEnhancing HighSpeed Telecommunications Networks with FEC
White Paper Enhancing HighSpeed Telecommunications Networks with FEC As the demand for highbandwidth telecommunications channels increases, service providers and equipment manufacturers must deliver
More informationThe processor can usually address a memory space that is much larger than the memory space covered by an individual memory chip.
Memory ddress Decoding The processor can usually address a memory space that is much larger than the memory space covered by an individual memory chip. In order to splice a memory device into the address
More informationVLSI Architecture for DCT Based On High Quality DA
International Journal of Engineering and Technical Research (IJETR) ISSN: 23210869, Volume2, Issue6, June 2014 VLSI Architecture for DCT Based On High Quality DA Urbi Sharma, Tarun Verma, Rita Jain
More informationAn Efficient Majority Logic Fault Detection to reduce the Accessing time for Memory Applications
International Journal of Scientific and Research Publications, Volume 3, Issue 3, March 2013 1 An Efficient Majority Logic Fault Detection to reduce the Accessing time for Memory Applications R.Meenaakshi
More informationFiling Systems. Filing Systems
Filing Systems At the outset we identified longterm storage as desirable characteristic of an OS. EG: Online storage for an MIS. Convenience of not having to rewrite programs. Sharing of data in an
More informationAN INTRODUCTION TO ERROR CORRECTING CODES Part 1
AN INTRODUCTION TO ERROR CORRECTING CODES Part 1 Jack Keil Wolf ECE 154C Spring 2008 Noisy Communications Noise in a communications channel can cause errors in the transmission of binary digits. Transmit:
More informationImplementation and Design of AES SBox on FPGA
International Journal of Research in Engineering and Science (IJRES) ISSN (Online): 2329364, ISSN (Print): 2329356 Volume 3 Issue ǁ Jan. 25 ǁ PP.94 Implementation and Design of AES SBox on FPGA Chandrasekhar
More informationEngineering Change Order (ECO) Support in Programmable Logic Design
White Paper Engineering Change Order (ECO) Support in Programmable Logic Design A major benefit of programmable logic is that it accommodates changes to the system specification late in the design cycle.
More informationMICROPROCESSOR. Exclusive for IACE Students www.iace.co.in iacehyd.blogspot.in Ph: 9700077455/422 Page 1
MICROPROCESSOR A microprocessor incorporates the functions of a computer s central processing unit (CPU) on a single Integrated (IC), or at most a few integrated circuit. It is a multipurpose, programmable
More informationData Storage  II: Efficient Usage & Errors. Contains slides from: Naci Akkök, Hector GarciaMolina, Pål Halvorsen, Ketil Lund
Data Storage  II: Efficient Usage & Errors Contains slides from: Naci Akkök, Hector GarciaMolina, Pål Halvorsen, Ketil Lund Overview Efficient storage usage Disk errors Error recovery INF3 7.3.26 Ellen
More informationIntroduction to Simulation of Verilog Designs. 1 Introduction. For Quartus II 14.0
Introduction to Simulation of Verilog Designs For Quartus II 14.0 1 Introduction An effective way of determining the correctness of a logic circuit is to simulate its behavior. This tutorial provides an
More informationFault Tolerance & Reliability CDA 5140. Chapter 3 RAID & Sample Commercial FT Systems
Fault Tolerance & Reliability CDA 5140 Chapter 3 RAID & Sample Commercial FT Systems  basic concept in these, as with codes, is redundancy to allow system to continue operation even if some components
More informationDESIGN AND PERFORMANCE ANALYSIS OF CMOS FULL ADDER WITH 14 TRANSISTOR
DESIGN AND PERFORMANCE ANALYSIS OF CMOS FULL ADDER WITH 14 TRANSISTOR 1 Ruchika Sharma, 2 Rajesh Mehra 1 ME student, NITTTR, Chandigarh,India 2 Associate Professor, NITTTR, Chandigarh,India 1 just_ruchika016@yahoo.co.in
More informationFPGA IMPLEMENTATION OF 4DPARITY BASED DATA CODING TECHNIQUE
FPGA IMPLEMENTATION OF 4DPARITY BASED DATA CODING TECHNIQUE Vijay Tawar 1, Rajani Gupta 2 1 Student, KNPCST, Hoshangabad Road, Misrod, Bhopal, Pin no.462047 2 Head of Department (EC), KNPCST, Hoshangabad
More informationDESIGN OF MULTISTANDARD TRANSFORM CORE USING COMMON SHARING DISTRIBUTED ARITHMETIC
Int. J. Elec&Electr.Eng&Telecoms. 2015 A Bharathi et al., 2015 Research Paper ISSN 2319 2518 www.ijeetc.com Special Issue, Vol. 1, No. 1, March 2015 National Level Technical Conference P&E BiDD2015 2015
More informationPN Generators Using the SRL Macro Author: Andy Miller and Michael Gulotta
Application Note: Virtex Series, VirtexII Series, and SpartanII Family XAPP2 (v.2) June 4, 24 R Author: Andy Miller and Michael Gulotta Summary Pseudorandom Noise (PN) generators are at the heart of
More informationRead this before starting!
Points missed: Student's Name: Total score: /100 points East Tennessee State University Department of Computer and Information Sciences CSCI 4717 Computer Architecture TEST 2 for Fall Semester, 2006 Section
More informationIJESRT. [Padama, 2(5): May, 2013] ISSN: 22779655
IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY Design and Verification of VLSI Based AES Crypto Core Processor Using Verilog HDL Dr.K.Padama Priya *1, N. Deepthi Priya 2 *1,2
More informationOverview. How distributed file systems work Part 1: The code repair problem Regenerating Codes. Part 2: Locally Repairable Codes
Overview How distributed file systems work Part 1: The code repair problem Regenerating Codes Part 2: Locally Repairable Codes Part 3: Availability of Codes Open problems 1 current hadoop architecture
More informationLinear Codes. Chapter 3. 3.1 Basics
Chapter 3 Linear Codes In order to define codes that we can encode and decode efficiently, we add more structure to the codespace. We shall be mainly interested in linear codes. A linear code of length
More informationLaboratory Exercise 3
Laboratory Exercise 3 Latches, Flipflops, and egisters The purpose of this exercise is to investigate latches, flipflops, and registers. Part I Altera FPGAs include flipflops that are available for
More informationModeling Sequential Elements with Verilog. Prof. ChienNan Liu TEL: 034227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit
Modeling Sequential Elements with Verilog Prof. ChienNan Liu TEL: 034227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 41 Sequential Circuit Outputs are functions of inputs and present states of storage elements
More information512B/513B Transcoding and FEC for 100 Gb/s Backplane and Copper Links
512B/513B Transcoding and FEC for 0 Gb/s Backplane and Copper Links IEEE 802.3 0 Gb/s Backplane and Copper Cable Study Group Chicago, September 1314, 2011 Roy Cideciyan  Motivation for 512B/513B transcoding
More informationFunctionalRepairbyTransfer Regenerating Codes
FunctionalRepairbyTransfer Regenerating Codes Kenneth W Shum and Yuchong Hu Abstract In a distributed storage system a data file is distributed to several storage nodes such that the original file can
More informationDigital System Design. Digital System Design with Verilog
Digital System Design with Verilog Adapted from Z. Navabi Portions Copyright Z. Navabi, 2006 1 Digital System Design Automation with Verilog Digital Design Flow Design entry Testbench in Verilog Design
More informationLecture 2: The Complexity of Some Problems
IAS/PCMI Summer Session 2000 Clay Mathematics Undergraduate Program Basic Course on Computational Complexity Lecture 2: The Complexity of Some Problems David Mix Barrington and Alexis Maciel July 18, 2000
More informationELECTENG702 Advanced Embedded Systems. Improving AES128 software for Altera Nios II processor using custom instructions
Assignment ELECTENG702 Advanced Embedded Systems Improving AES128 software for Altera Nios II processor using custom instructions October 1. 2005 Professor Zoran Salcic by Kilian Foerster 108 Claybrook
More information1. A Sequential Parity Checker
Chapter 13: Analysis of Clocked Sequential Circuits 1. A Sequential Parity Checker When binary data is transmitted or stored, an extra bit (called a parity bit) is frequently added for purposes of error
More informationThe mathematics of RAID6
The mathematics of RAID6 H. Peter Anvin First version 20 January 2004 Last updated 20 December 2011 RAID6 supports losing any two drives. syndromes, generally referred P and Q. The way
More informationChapter 13. Chapter Outline. Disk Storage, Basic File Structures, and Hashing
Chapter 13 Disk Storage, Basic File Structures, and Hashing Copyright 2007 Ramez Elmasri and Shamkant B. Navathe Chapter Outline Disk Storage Devices Files of Records Operations on Files Unordered Files
More informationENEE245 Digital Circuits and Systems Lab Manual
ENEE245 Digital Circuits and Systems Lab Manual Department of Engineering, Physical & Computer Sciences Montgomery College Version 1.2 Copyright Prof. Lan Xiang (Do not distribute without permission) 1
More informationIntroduction to Computer Networks. Codes  Notations. Error Detecting & Correcting Codes. Parity. TwoDimensional Bit Parity
Introduction to Computer Networks Error Detecting & Correcting Codes Codes  Notations K bits of data encoded into n bits of information. nk bits of redundancy The information data is of length K The
More informationR&D White Paper WHP 031. ReedSolomon error correction. Research & Development BRITISH BROADCASTING CORPORATION. July 2002. C.K.P.
R&D White Paper WHP 03 July 00 Reedolomon error correction C.K.P. Clarke Research & Deelopment BRITIH BROADCATING CORPORATION BBC Research & Deelopment White Paper WHP 03 Reedolomon Error Correction
More informationUsing RAID6 for Advanced Data Protection
Using RAI6 for Advanced ata Protection 2006 Infortrend Corporation. All rights reserved. Table of Contents The Challenge of Fault Tolerance... 3 A Compelling Technology: RAI6... 3 Parity... 4 Why Use RAI6...
More informationPIONEER RESEARCH & DEVELOPMENT GROUP
SURVEY ON RAID Aishwarya Airen 1, Aarsh Pandit 2, Anshul Sogani 3 1,2,3 A.I.T.R, Indore. Abstract RAID stands for Redundant Array of Independent Disk that is a concept which provides an efficient way for
More informationLaboratory Exercise 3
Laboratory Exercise 3 Latches, Flipflops, and egisters The purpose of this exercise is to investigate latches, flipflops, and registers. Part I Altera FPGAs include flipflops that are available for
More informationImproved NAND Flash Memories Storage Reliablity Using Nonlinear Multi Error Correction Codes
Advance in Electronic and Electric Engineering. ISSN 22311297, Volume 3, Number 9 (2013), pp. 11211134 Research India Publications http://www.ripublication.com/aeee.htm Improved NAND Flash Memories Storage
More informationComputer Systems Structure Main Memory Organization
Computer Systems Structure Main Memory Organization Peripherals Computer Central Processing Unit Main Memory Computer Systems Interconnection Communication lines Input Output Ward 1 Ward 2 Storage/Memory
More informationVIOLA  A Scalable and FaultTolerant VideoonDemand System
VIOLA  A Scalable and FaultTolerant VideoonDemand System Y.B. Lee Information Networking Laboratories Faculty of Engineering The Chinese University of Hong Kong Tel:(852)26037360 Fax:(852)26037327
More informationNote: Correction to the 1997 Tutorial on ReedSolomon Coding
Note: Correction to the 1997 utorial on ReedSolomon Coding James S Plank Ying Ding University of ennessee Knoxville, N 3799 [plank,ying]@csutkedu echnical Report UCS03504 Department of Computer Science
More informationConsider a 4M x 1 bit RAM. It will apparently need a 22 to4m decoder. 4 million output lines will make it complex! D in. D out
Inside RAM Twolevel addressing Consider a 4M x bit RAM. It will apparently need a 22 to4m decoder. 4 million output lines will make it complex! Complex! Twlevel addressing simplifies it. A2A These
More informationWhy disk arrays? CPUs speeds increase faster than disks.  Time won t really help workloads where disk in bottleneck
1/19 Why disk arrays? CPUs speeds increase faster than disks  Time won t really help workloads where disk in bottleneck Some applications (audio/video) require big files Disk arrays  make one logical
More informationInBlock Level Redundancy Management for Flash Storage System
, pp.309318 http://dx.doi.org/10.14257/ijmue.2015.10.9.32 InBlock Level Redundancy Management for Flash Storage System SeungHo Lim Division of Computer and Electronic Systems Engineering Hankuk University
More informationDigital Systems Design! Lecture 1  Introduction!!
ECE 3401! Digital Systems Design! Lecture 1  Introduction!! Course Basics Classes: Tu/Th 1112:15, ITE 127 Instructor Mohammad Tehranipoor Office hours: T 12pm, or upon appointments @ ITE 441 Email:
More informationParallel AES Encryption with Modified Mixcolumns For Many Core Processor Arrays M.S.Arun, V.Saminathan
Parallel AES Encryption with Modified Mixcolumns For Many Core Processor Arrays M.S.Arun, V.Saminathan Abstract AES is an encryption algorithm which can be easily implemented on fine grain many core systems.
More informationLoad Balancing in Fault Tolerant Video Server
Load Balancing in Fault Tolerant Video Server # D. N. Sujatha*, Girish K*, Rashmi B*, Venugopal K. R*, L. M. Patnaik** *Department of Computer Science and Engineering University Visvesvaraya College of
More informationClick on the diagram to see RAID 0 in action
Click on the diagram to see RAID 0 in action RAID Level 0 requires a minimum of 2 drives to implement RAID 0 implements a striped disk array, the data is broken down into blocks and each block is written
More informationManoranjan Pradhan Deptt. Of El&TC Engg Vssut,Burla, Odisha India
Volume 3, Issue 12, December 2013 ISSN: 2277 128X International Journal of Advanced Research in Computer Science and Software Engineering Research Paper Available online at: www.ijarcsse.com Control Unit
More informationPolymorphic AES Encryption Implementation
Polymorphic AE Encryption Implementation Ricardo Chaves, Leonel ousa Instituto uperior Técnico / INECID Portugal, Lisbon Email: ricardo.chaves@inescid.pt Georgi Kuzmanov, tamatis Vassiliadis Computer
More informationDesign of a Highspeed and largecapacity NAND Flash storage system based on Fiber Acquisition
Design of a Highspeed and largecapacity NAND Flash storage system based on Fiber Acquisition Qing Li, Shanqing Hu * School of Information and Electronic Beijing Institute of Technology Beijing, China
More information9/14/2011 14.9.2011 8:38
Algorithms and Implementation Platforms for Wireless Communications TLT9706/ TKT9636 (Seminar Course) BASICS OF FIELD PROGRAMMABLE GATE ARRAYS Waqar Hussain firstname.lastname@tut.fi Department of Computer
More informationHardware: Input, Processing, and Output Devices
Hardware: Input, Processing, and Output Devices Computer Systems Hardware Components Execution of an Instruction Processing Characteristics and Functions Physical Characteristics of CPU Memory Characteristics
More informationHP Smart Array Controllers and basic RAID performance factors
Technical white paper HP Smart Array Controllers and basic RAID performance factors Technology brief Table of contents Abstract 2 Benefits of drive arrays 2 Factors that affect performance 2 HP Smart Array
More informationQuartus II Software Design Series : Foundation. Digitale Signalverarbeitung mit FPGA. Digitale Signalverarbeitung mit FPGA (DSF) Quartus II 1
(DSF) Quartus II Stand: Mai 2007 Jens Onno Krah Cologne University of Applied Sciences www.fhkoeln.de jens_onno.krah@fhkoeln.de Quartus II 1 Quartus II Software Design Series : Foundation 2007 Altera
More informationMagnus: Peer to Peer Backup System
Magnus: Peer to Peer Backup System Naveen Gattu, Richard Huang, John Lynn, Huaxia Xia Department of Computer Science University of California, San Diego Abstract Magnus is a peertopeer backup system
More informationIMPLEMENTATION ENHANCED MAJORITY LOGIC DECODING OF EUCLIDEAN GEOMETRY LOW DENSITY PARITY CHECK (EGLDPC) CODES FOR ERROR DETECTION
IMPLEMENTATION ENHANCED MAJORITY LOGIC DECODING OF EUCLIDEAN GEOMETRY LOW DENSITY PARITY CHECK (EGLDPC) CODES FOR ERROR DETECTION 1 Vittalam.D.Kumar Reddy M.Tech, VLSI System Design, 2 P.Giri Babu, Asst.
More informationLossless Greyscale Image Compression using Source Symbols Reduction and Huffman Coding
Lossless Greyscale Image Compression using Source Symbols Reduction and Huffman Coding C. SARAVANAN cs@cc.nitdgp.ac.in Assistant Professor, Computer Centre, National Institute of Technology, Durgapur,WestBengal,
More informationErasure Codes Made So Simple, You ll Really Like Them
Erasure Codes Made So Simple, You ll Really Like Them W. David Schwaderer August 7, 214 schwaderer_1@comcast.net Santa Clara, CA 1 Agenda Errors Versus Erasures HDD Bit Error Rate Implications RAID 4,
More informationNonRedundant (RAID Level 0)
There are many types of RAID and some of the important ones are introduced below: NonRedundant (RAID Level 0) A nonredundant disk array, or RAID level 0, has the lowest cost of any RAID organization
More informationWhat Types of ECC Should Be Used on Flash Memory?
What Types of ECC Should Be Used on Flash Memory? Application 1. Abstract NOR Flash normally does not need ECC (ErrorCorrecting Code). On the other hand, NAND requires ECC to ensure data integrity. NAND
More informationFPGA Implementation of IP Packet Segmentation and Reassembly in Internet Router*
SERBIAN JOURNAL OF ELECTRICAL ENGINEERING Vol. 6, No. 3, December 2009, 399407 UDK: 004.738.5.057.4 FPGA Implementation of IP Packet Segmentation and Reassembly in Internet Router* Marko Carević 1,a,
More informationModule 6. Channel Coding. Version 2 ECE IIT, Kharagpur
Module 6 Channel Coding Lesson 35 Convolutional Codes After reading this lesson, you will learn about Basic concepts of Convolutional Codes; State Diagram Representation; Tree Diagram Representation; Trellis
More informationAutomata Designs for Data Encryption with AES using the Micron Automata Processor
IJCSNS International Journal of Computer Science and Network Security, VOL.15 No.7, July 2015 1 Automata Designs for Data Encryption with AES using the Micron Automata Processor Angkul Kongmunvattana School
More informationA Performance Comparison of OpenSource Erasure Coding Libraries for Storage Applications
A Performance Comparison of OpenSource Erasure Coding Libraries for Storage Applications Catherine D. Schuman James S. Plank Technical Report UTCS8625 Department of Electrical Engineering and Computer
More informationDevelopment of a data reading device for a CDROM drive with FPGA technology
Development of a data reading device for a CDROM drive with FPGA technology P. Nanthanavoot and P. Chongstitvatana Department of Computer Engineering, Faculty of Engineering, Chulalongkorn University,
More informationManagement Challenge. Managing Hardware Assets. Central Processing Unit. What is a Computer System?
Management Challenge Managing Hardware Assets What computer processing and storage capability does our organization need to handle its information and business transactions? What arrangement of computers
More informationAims and Objectives. E 3.05 Digital System Design. Course Syllabus. Course Syllabus (1) Programmable Logic
Aims and Objectives E 3.05 Digital System Design Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ Email: p.cheung@ic.ac.uk How to go
More informationManchester EncoderDecoder for Xilinx CPLDs
Application Note: CoolRunner CPLDs R XAPP339 (v.3) October, 22 Manchester EncoderDecoder for Xilinx CPLDs Summary This application note provides a functional description of VHDL and Verilog source code
More informationAltera Quartus II Tutorial. CSE140L WI06 TA: Jianhua Liu CSE Dept. UCSD
Altera Quartus II Tutorial CSE140L WI06 TA: Jianhua Liu CSE Dept. UCSD Altera Quartus II The Quartus II development software provides a complete design environment for FPGA designs. Design entry using
More informationNonlinear MultiError Correction Codes for Reliable NAND Flash Memories
1 Nonlinear MultiError Correction Codes for Reliable NAND Flash Memories Zhen Wang, Student Member, IEEE, Mark Karpovsky, Fellow, IEEE, and Ajay Joshi, Member, IEEE Abstract Multilevel cell (MLC NAND
More informationOn the Use of Strong BCH Codes for Improving Multilevel NAND Flash Memory Storage Capacity
On the Use of Strong BCH Codes for Improving Multilevel NAND Flash Memory Storage Capacity Fei Sun, Ken Rose, and Tong Zhang ECSE Department, Rensselaer Polytechnic Institute, USA Abstract This paper investigates
More informationLecture N 1 PHYS 3330. Microcontrollers
Lecture N 1 PHYS 3330 Microcontrollers If you need more than a handful of logic gates to accomplish the task at hand, you likely should use a microcontroller instead of discrete logic gates 1. Microcontrollers
More informationThe Development of ErrorCorrecting Codes
The Development of ErrorCorrecting Codes Chair Prof. TrieuKien Truong IEEE Fellow, and Editor, IEEE Transactions on Communications Department of Information Engineering, IShou University, Kaohsiung
More informationTransparent D FlipFlop
Transparent FlipFlop The RS flipflop forms the basis of a number of 1bit storage devices in digital electronics. ne such device is shown in the figure, where extra combinational logic converts the input
More informationECEN 5682 Theory and Practice of Error Control Codes
ECEN 5682 Theory and Practice of Error Control Codes Convolutional Codes University of Colorado Spring 2007 Linear (n, k) block codes take k data symbols at a time and encode them into n code symbols.
More informationA Practical Approach of Storage Strategy for Grid Computing Environment
A Practical Approach of Storage Strategy for Grid Computing Environment Kalim Qureshi Abstract  An efficient and reliable fault tolerance protocol plays an important role in making the system more stable.
More informationSurviving Two Disk Failures. Introducing Various RAID 6 Implementations
Surviving Two Failures Introducing Various RAID 6 Implementations Notices The information in this document is subject to change without notice. While every effort has been made to ensure that all information
More information