Gamma-ray Large Area Space Telescope (GLAST) Large Area Telescope (LAT) Calorimeter AFEE Board Parts Radiation Test Plan

Transcription

1 GLAST LAT DESIGN DESCRIPTION Document Title AFEE Board Parts Radiation Test Plan Document # Date Effective LAT-SS April 2003 Prepared by(s) Supersedes James Ampe None Subsystem/Office Calorimeter Subsystem Gamma-ray Large Area Space Telescope (GLAST) Large Area Telescope (LAT) Calorimeter AFEE Board Parts Radiation Test Plan

2 LAT-SS AFEE Board Parts Radiation Test Plan Page 2 of 12 DOCUMENT APPROVAL Prepared by: James Ampe CAL Electrical Lead Engineer Date Nick Virmani CAL Flight Assurance Manager Date Approved by: Gunther Haller LAT Electronics Manager Date W. Neil Johnson CAL Subsystem Manager Date

3 LAT-SS AFEE Board Parts Radiation Test Plan Page 3 of 12 CHANGE HISTORY LOG Revision Effective Date Description of Changes 4/1/03 Initial Release

4 LAT-SS AFEE Board Parts Radiation Test Plan Page 4 of 12 Table of Contents Table of Contents...4 List of Figures...5 List of Tables PURPOSE SCOPE DEFINITIONS Acronyms Definitions APPLICABLE DOCUMENTS References Conceptual Design Documents INTRODUCTION Latchup Testing...Error! Bookmark not defined. 6.1 Single Event Upset Testing Total Dose Testing...11

5 LAT-SS AFEE Board Parts Radiation Test Plan Page 5 of 12 List of Figures Figure 1. Latchup Testing Setetup....8 Figure 2. Cal Radiation Test Board Layout Diagram....8 Figure 3. Latchup Protection Circuit per Type of Device...9 List of Tables Table 1. Upset Classification and Testing Method....10

6 LAT-SS AFEE Board Parts Radiation Test Plan Page 6 of 12 1 PURPOSE This document describes the radiation testing that will be performed on the electronics components that will be used for the flight calorimeter instrument. This testing is a necessary for assuring the flight worthiness of these electronic components. 2 SCOPE This document provide a detailed description of the latchup testing and total dose testing to be performed on the GCFE ASIC, GCRC ASIC, MAX145 ADC, MAX5121 DAC, and LM V reference. 3 DEFINITIONS 3.1 Acronyms GLAST Gamma-ray Large Area Space Telescope CAL Calorimeter Detector ASIC Application Specific Integrated Circuit GCFE Glast Calorimeter Front end ASIC GCRC Glast Calorimeter Readout Controller SEL Single Event Latchup SEU Single Event Upset (Not Latchup, data upset only) SEE Single Event Effect (Latchup or upset) TID Total Ionizing Dose LET Linear Energy Transfer MeV Mega Electron Volt CMOS Complimentary Metal Oxide Semiconductor DUT Device Under Test ADC Analog to Digital Converter DAC Digital to Analog Converter HE High Energy LE Low Energy 3.2 Definitions µsec, µs Microsecond, 10-6 second s, sec seconds 4 APPLICABLE DOCUMENTS Documents that are relevant to the development of the GCFE concept and its requirements include the following: 433-SPEC-0001 GLAST Mission Systems Specification, CH References

7 LAT-SS AFEE Board Parts Radiation Test Plan Page 7 of Conceptual Design Documents [1] GLAST Calorimeter Analog Front-End ASIC Design Consideration, Neil Johnson, NRL. [2] Design Description of the Glast Calorimeter Front-End Electronics (GCFE) ASIC, LAT-SS D3. [3] Conceptual Design of the GLAST Calorimeter Readout Control (GCRC) ASIC, LAT-SS D4. 5 INTRODUCTION The Calorimeter active electonics are comprised of a custom analog GCFE ASIC, custom digital GCRC ASIC, commercial analog to digital converter (ADC) Maxim MAX145, commercial digital to analog converter (DAC) Maxim MAX5121, and a military 2.5 volt reference National LM185. The radiation requirements for the calorimeter componets are latchup insensivity < 37 MeV(mg/cm^2). Total dose expected for the GLAST orbit over a 5 year mission is 5 krad. All flight electronic components are purchased as single lots. Radiation testing of flight components is performed on a per-lot basis. Latchup and upset testing will be perfomed on a minimum of 3 components per device per lot. Latchup and upset testing will be peformed at a heavy ion facility with particles up to a LET 80 MeV(mg/cm^2). Total dose testing will be performed on a minimum of 3 components per device per lot. Total dose testing will be performed to a minimum of 10k rad, with measurements performed at sub-intervals. 6 Radiation Testing Latchup, single event upset, and total dose testing are detailed below. 6.1 Latchup Testing Latching testing will be performed at a facility that can accelerate heavy ions with sufficient energy to simulate the radiation environment in space. Brookhaven s Tandem Van De Graaff Accelerator, located in Long Island New York, has the capability of the following larger LET heavy ions: Gold, 346 MeV, LET 82 MeV/(mg/cm^2), penetration depth 28 um into silicon Iodine, 343 MeV, LET 60 MeV/(mg/cm^2), penetration depth 32.7 um into silicon Bromine, 280 MeV, LET 37.4 MeV/(mg/cm^2), pentration depth 36.2 um into silicon. The GCFE and GCRC custom ASICs are fabricated on HP s 0.5um epitaxial CMOS process. The Max145 and Max 5121 are produced on a bulk bipolar-cmos process Maxim Process S12EIFX. The LM185 is produced on a bulk bipolar process. The ion penetration depth into the silicon will be at least three times the active circuit depth. The test setup for heavy ion testing is shown in Figure 1. The test circuit board is mounted in a vacuum chamber, located at the end of an accelerator beam. A laser is selectable to be placed in the beam pipe to align the chip under test with the beam center. The ion beam illumination area is only large enough to irradiate one chip at a time. The test board is mounted on a X-Y linear stage with external controls enabling the test board to be re-positioned for irradiating any test chip on the board. A diagram of the testboard layout is shown in Figure 2. All devices to be tested are soldered in rows at the bottom of the circuit board. The digital controller and connectors reside at the top of the circuit board. All chips on the board to be tested are de-lidded prior to soldering. For handling protection of the delidded devices, a metal shield is kept over the delidded devices at all times except for the actual radiation testing. A diagram of the latchup protection detection and protection, per device type, is shown in Figure 3. The row of same devices has a current sensing resistor for which a high-side current sensor circuit determines the current drawn by the row. Each individual chip has another small current protection resistor. A latchup is determined when the row current is increased by 3 times the nominal current of any one device. Upon latchup determination, the digital controller shuts down power to the row, and disables the row signal drivers, which would otherwise power the chips through the input

8 LAT-SS AFEE Board Parts Radiation Test Plan Page 8 of 12 protection diodes. After a period of time is allowed for the latch to clear, the controller then brings the power and control signals back up. Testing in the ion beam is then resumed. The controller also outputs digital signals which can be used to stop the beam upon occurrence of latchup. This beam gating enables accurate ion fluence counts per latchup. Figure 1. Latchup Testing Setetup. Test Circuit Board Vacuum Chamber Beam Source Beam Stop, Laser Alignment Chips Under Test Analog Test Points Power Supply PC Computer Parallel Port Vertical and Horizontal Linear Motion Stage Mounted on Rotating Platform. Figure 2. Cal Radiation Test Board Layout Diagram. Power/Signal Connectors Digital Control FPGA LM185 TO-5 MAX5121 Chips MAX145 Chips GCFE Chips GCRC Chips

9 LAT-SS AFEE Board Parts Radiation Test Plan Page 9 of 12 Figure 3. Latchup Detection and Protection Circuit per Type of Device. Enable Supply Voltage Power Switch Current Sense Resistor DUT Power Supply Digital Control Enable Tristatable Driver Bussed Control Over Current Indicator High Side Current Sense DUT A DUT B DUT C DUT D Individual Outputs Latchup Indicator

10 LAT-SS AFEE Board Parts Radiation Test Plan Page 10 of Single Event Upset Testing The same testboard and test facility used for latchup testing will be used for single event upset testing. Single event upset testing will be performed concurrently with latchup testing. Ion energy will be lowered until no upsets are detected per device type. The following is our classification of upset, per device tested: Table 1. Upset Classification and Testing Method. Possible Upset Devices Test Method Testboard Implementation Register Value Change Load Register Value Change DAC Output Register Change State Machine Stuck at wrong state Incorrect Conversion Value Incorrect Reference Voltage. GCFE, GCRC Max5121 DAC Max5121 DAC GCFE, GCRC Max145 ADC LM185 Reference Write register value once. Read continuously for changed value. Write data value periodically and examine shifted-out value for change. Monitor analog output of DAC for change that does not return to nominal state. Command devices through all states and make sure that device does not get stuck in non-recoverable state. Continually perform conversions on fixed analog input, look for returned values outside of the noise distribution. Continually monitor reference voltage for value stuck outside of nominal voltage. Each GCFE and GCRC is hard wired to a different address. Each chip is individually readable. The controller periodically writes the same 16 bit value to the DACs and compares the shifted back value. Each DAC voltage output is brought out and connected to voltmeter. The GCFE and GCRC chips will be commanded through event readout states. Output data will be examined to verify state machines do not get stuck in a nonrecoverable state. The ADC conversion value will be histogrammed, looking for outlier data. The reference voltage will be brought out to a voltmeter.

11 LAT-SS AFEE Board Parts Radiation Test Plan Page 11 of Total Dose Testing Total dose testing will be performed with the chips irriated with a colbalt 60 gamma ray source. The chips will be biased at nominal voltage during this procedure. The chips will be removed from the radiation source and tested at sub-intervals of dosage. The total dose testing will be performed up to at least 10 kilorad. Characteristic to Be Tested Specific Devices To Test Method of Test Noise GCFE Perform linear sweep of charge injection, and create plot of noise vs. injection charge. Perform for all 4 ranges. Linearity GCFE Perform linear sweep of charge injection, and create plot of amplitude vs. injection charge. Perform for all 4 ranges. Preamp Gain GCFE With large 100pF capacitance on each HE and LE input, inject known charge into preamp amd measure shaper peak output voltage. DAC Output Voltage Drift DAC Output Voltage Drift GCFE Max5121 DAC Command GCFE Reference DAC to be output. Test output voltage at selected programmed settings. Command DAC to selected programmed settings and measure output voltage. Analog Output Drive Max5121 Decrease load resistance and plot output voltage vs. load resistance. Analog Output Settling Time LVDS Output Current Drive LVDS Receiver Delay CMOS Drive Delay ADC Conversion Value ADC Conversion Time Supply Current GCFE GCFE, GCRC GCFE, GCRC GCRC, Max145, Max5121 Max145 ADC Max145 GCFE, GCRC, Max145, Max5121 With known resistive and capacitive load, measure settling time in output changing from minimum to maximum value, and maximum to minimum value. With known resistive termination on LVDS drive lines, measure peak peak deviation of comunication lines to determine output current drive. Also measure time from voltage minimum to voltage maximum. Apply LVDS signal to input receiver, examine time delay to output. Control DUT to change state of CMOS output with fixed resistive and capacitive load. Measure fall time and rise time. Apply known analog input to ADC and collect histogram of conversion values. Check histogram for peak shift and spread. Perform conversions with internal conversion clock. Monitor data line for time toconversion complete. Measure supply current a quiescent state. Reference Voltage LM185 Measure reference voltage output.

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